33 	xhci_dbg(xhci, "// xHCI capability registers at %p:\n",  in xhci_dbg_regs()
36 	xhci_dbg(xhci, "// @%p = 0x%x (CAPLENGTH AND HCIVERSION)\n",  in xhci_dbg_regs()
38 	xhci_dbg(xhci, "//   CAPLENGTH: 0x%x\n",  in xhci_dbg_regs()
41 	xhci_dbg(xhci, "//   HCIVERSION: 0x%x\n",  in xhci_dbg_regs()
45 	xhci_dbg(xhci, "// xHCI operational registers at %p:\n", xhci->op_regs);  in xhci_dbg_regs()
48 	xhci_dbg(xhci, "// @%p = 0x%x RTSOFF\n",  in xhci_dbg_regs()
51 	xhci_dbg(xhci, "// xHCI runtime registers at %p:\n", xhci->run_regs);  in xhci_dbg_regs()
54 	xhci_dbg(xhci, "// @%p = 0x%x DBOFF\n", &xhci->cap_regs->db_off, temp);  in xhci_dbg_regs()
55 	xhci_dbg(xhci, "// Doorbell array at %p:\n", xhci->dba);  in xhci_dbg_regs()
63 	xhci_dbg(xhci, "xHCI capability registers at %p:\n", xhci->cap_regs);  in xhci_print_cap_regs()
67 	xhci_dbg(xhci, "CAPLENGTH AND HCIVERSION 0x%x:\n",  in xhci_print_cap_regs()
69 	xhci_dbg(xhci, "CAPLENGTH: 0x%x\n",  in xhci_print_cap_regs()
71 	xhci_dbg(xhci, "HCIVERSION: 0x%x\n", hci_version);  in xhci_print_cap_regs()
74 	xhci_dbg(xhci, "HCSPARAMS 1: 0x%x\n",  in xhci_print_cap_regs()
76 	xhci_dbg(xhci, "  Max device slots: %u\n",  in xhci_print_cap_regs()
78 	xhci_dbg(xhci, "  Max interrupters: %u\n",  in xhci_print_cap_regs()
80 	xhci_dbg(xhci, "  Max ports: %u\n",  in xhci_print_cap_regs()
84 	xhci_dbg(xhci, "HCSPARAMS 2: 0x%x\n",  in xhci_print_cap_regs()
86 	xhci_dbg(xhci, "  Isoc scheduling threshold: %u\n",  in xhci_print_cap_regs()
88 	xhci_dbg(xhci, "  Maximum allowed segments in event ring: %u\n",  in xhci_print_cap_regs()
92 	xhci_dbg(xhci, "HCSPARAMS 3 0x%x:\n",  in xhci_print_cap_regs()
94 	xhci_dbg(xhci, "  Worst case U1 device exit latency: %u\n",  in xhci_print_cap_regs()
96 	xhci_dbg(xhci, "  Worst case U2 device exit latency: %u\n",  in xhci_print_cap_regs()
100 	xhci_dbg(xhci, "HCC PARAMS 0x%x:\n", (unsigned int) temp);  in xhci_print_cap_regs()
101 	xhci_dbg(xhci, "  HC generates %s bit addresses\n",  in xhci_print_cap_regs()
103 	xhci_dbg(xhci, "  HC %s Contiguous Frame ID Capability\n",  in xhci_print_cap_regs()
105 	xhci_dbg(xhci, "  HC %s generate Stopped - Short Package event\n",  in xhci_print_cap_regs()
108 	xhci_dbg(xhci, "  FIXME: more HCCPARAMS debugging\n");  in xhci_print_cap_regs()
111 	xhci_dbg(xhci, "RTSOFF 0x%x:\n", temp & RTSOFF_MASK);  in xhci_print_cap_regs()
116 		xhci_dbg(xhci, "HCC PARAMS2 0x%x:\n", (unsigned int) temp);  in xhci_print_cap_regs()
117 		xhci_dbg(xhci, "  HC %s Force save context capability",  in xhci_print_cap_regs()
119 		xhci_dbg(xhci, "  HC %s Large ESIT Payload Capability",  in xhci_print_cap_regs()
121 		xhci_dbg(xhci, "  HC %s Extended TBC capability",  in xhci_print_cap_regs()
131 	xhci_dbg(xhci, "USBCMD 0x%x:\n", temp);  in xhci_print_command_reg()
132 	xhci_dbg(xhci, "  HC is %s\n",  in xhci_print_command_reg()
134 	xhci_dbg(xhci, "  HC has %sfinished hard reset\n",  in xhci_print_command_reg()
136 	xhci_dbg(xhci, "  Event Interrupts %s\n",  in xhci_print_command_reg()
138 	xhci_dbg(xhci, "  Host System Error Interrupts %s\n",  in xhci_print_command_reg()
140 	xhci_dbg(xhci, "  HC has %sfinished light reset\n",  in xhci_print_command_reg()
149 	xhci_dbg(xhci, "USBSTS 0x%x:\n", temp);  in xhci_print_status()
150 	xhci_dbg(xhci, "  Event ring is %sempty\n",  in xhci_print_status()
152 	xhci_dbg(xhci, "  %sHost System Error\n",  in xhci_print_status()
154 	xhci_dbg(xhci, "  HC is %s\n",  in xhci_print_status()
160 	xhci_dbg(xhci, "xHCI operational registers at %p:\n", xhci->op_regs);  in xhci_print_op_regs()
181 			xhci_dbg(xhci, "%p port %s reg = 0x%x\n",  in xhci_print_ports()
201 	xhci_dbg(xhci, "  %p: ir_set[%i]\n", ir_set, set_num);  in xhci_print_ir_set()
203 	xhci_dbg(xhci, "  %p: ir_set.pending = 0x%x\n", addr,  in xhci_print_ir_set()
208 	xhci_dbg(xhci, "  %p: ir_set.control = 0x%x\n", addr,  in xhci_print_ir_set()
213 	xhci_dbg(xhci, "  %p: ir_set.erst_size = 0x%x\n", addr,  in xhci_print_ir_set()
219 		xhci_dbg(xhci, "  WARN: %p: ir_set.rsvd = 0x%x\n",  in xhci_print_ir_set()
224 	xhci_dbg(xhci, "  %p: ir_set.erst_base = @%08llx\n",  in xhci_print_ir_set()
229 	xhci_dbg(xhci, "  %p: ir_set.erst_dequeue = @%08llx\n",  in xhci_print_ir_set()
238 	xhci_dbg(xhci, "xHCI runtime registers at %p:\n", xhci->run_regs);  in xhci_print_run_regs()
240 	xhci_dbg(xhci, "  %p: Microframe index = 0x%x\n",  in xhci_print_run_regs()
246 			xhci_dbg(xhci, "  WARN: %p: Rsvd[%i] = 0x%x\n",  in xhci_print_run_regs()
263 		xhci_dbg(xhci, "Offset 0x%x = 0x%x\n",  in xhci_print_trb_offsets()
277 		xhci_dbg(xhci, "Link TRB:\n");  in xhci_debug_trb()
281 		xhci_dbg(xhci, "Next ring segment DMA address = 0x%llx\n", address);  in xhci_debug_trb()
283 		xhci_dbg(xhci, "Interrupter target = 0x%x\n",  in xhci_debug_trb()
285 		xhci_dbg(xhci, "Cycle bit = %u\n",  in xhci_debug_trb()
287 		xhci_dbg(xhci, "Toggle cycle bit = %u\n",  in xhci_debug_trb()
289 		xhci_dbg(xhci, "No Snoop bit = %u\n",  in xhci_debug_trb()
298 		xhci_dbg(xhci, "DMA address or buffer contents= %llu\n", address);  in xhci_debug_trb()
302 		xhci_dbg(xhci, "Command TRB pointer = %llu\n", address);  in xhci_debug_trb()
303 		xhci_dbg(xhci, "Completion status = %u\n",  in xhci_debug_trb()
305 		xhci_dbg(xhci, "Flags = 0x%x\n",  in xhci_debug_trb()
309 		xhci_dbg(xhci, "Unknown TRB with TRB type ID %u\n",  in xhci_debug_trb()
337 		xhci_dbg(xhci, "@%016llx %08x %08x %08x %08x\n", addr,  in xhci_debug_segment()
348 	xhci_dbg(xhci, "Ring deq = %p (virt), 0x%llx (dma)\n",  in xhci_dbg_ring_ptrs()
352 	xhci_dbg(xhci, "Ring deq updated %u times\n",  in xhci_dbg_ring_ptrs()
354 	xhci_dbg(xhci, "Ring enq = %p (virt), 0x%llx (dma)\n",  in xhci_dbg_ring_ptrs()
358 	xhci_dbg(xhci, "Ring enq updated %u times\n",  in xhci_dbg_ring_ptrs()
379 		xhci_dbg(xhci, "  Ring has not been updated\n");  in xhci_debug_ring()
396 			xhci_dbg(xhci, "Dev %d endpoint %d stream ID %d:\n",  in xhci_dbg_ep_rings()
404 		xhci_dbg(xhci, "Dev %d endpoint ring %d:\n",  in xhci_dbg_ep_rings()
418 		xhci_dbg(xhci, "@%016llx %08x %08x %08x %08x\n",  in xhci_dbg_erst()
433 	xhci_dbg(xhci, "// xHC command ring deq ptr low bits + flags = @%08x\n",  in xhci_dbg_cmd_ptrs()
435 	xhci_dbg(xhci, "// xHC command ring deq ptr high bits = @%08x\n",  in xhci_dbg_cmd_ptrs()
444 		xhci_dbg(xhci, "@%p (virt) @%08llx "  in dbg_rsvd64()
482 	xhci_dbg(xhci, "Slot Context:\n");  in xhci_dbg_slot_ctx()
483 	xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_info\n",  in xhci_dbg_slot_ctx()
487 	xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_info2\n",  in xhci_dbg_slot_ctx()
491 	xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - tt_info\n",  in xhci_dbg_slot_ctx()
495 	xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_state\n",  in xhci_dbg_slot_ctx()
500 		xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd[%d]\n",  in xhci_dbg_slot_ctx()
528 		xhci_dbg(xhci, "%s Endpoint %02d Context (ep_index %02d):\n",  in xhci_dbg_ep_ctx()
531 		xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - ep_info\n",  in xhci_dbg_ep_ctx()
535 		xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - ep_info2\n",  in xhci_dbg_ep_ctx()
539 		xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08llx - deq\n",  in xhci_dbg_ep_ctx()
543 		xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - tx_info\n",  in xhci_dbg_ep_ctx()
548 			xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd[%d]\n",  in xhci_dbg_ep_ctx()
578 		xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - drop flags\n",  in xhci_dbg_ctx()
582 		xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - add flags\n",  in xhci_dbg_ctx()
587 			xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd2[%d]\n",  in xhci_dbg_ctx()
610 	xhci_dbg(xhci, "%pV\n", &vaf);  in xhci_dbg_trace()