39 #define UDC_DEVCTL_ADDR		0x404	/* Device control */  macro
528 	pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);  in pch_udc_rmt_wakeup()
530 	pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);  in pch_udc_rmt_wakeup()
568 	pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);  in pch_udc_set_disconnect()
578 	pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);  in pch_udc_clear_disconnect()
579 	pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);  in pch_udc_clear_disconnect()
582 	pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);  in pch_udc_clear_disconnect()
601 	pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);  in pch_udc_reconnect()
602 	pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);  in pch_udc_reconnect()
605 	pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);  in pch_udc_reconnect()
760 		pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RDE);  in pch_udc_set_dma()
762 		pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_TDE);  in pch_udc_set_dma()
776 		pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RDE);  in pch_udc_clear_dma()
778 		pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_TDE);  in pch_udc_clear_dma()
788 	pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_CSR_DONE);  in pch_udc_set_csr_done()
1087 	pch_udc_bit_set(dev, UDC_DEVCTL_ADDR,  in pch_udc_init()