1945 	u32 scratch;  in defect7374_enable_data_eps_zero()  local
1949 	scratch = get_idx_reg(dev->regs, SCRATCH);  in defect7374_enable_data_eps_zero()
1951 	WARN_ON((scratch & (0xf << DEFECT7374_FSM_FIELD))  in defect7374_enable_data_eps_zero()
1954 	scratch &= ~(0xf << DEFECT7374_FSM_FIELD);  in defect7374_enable_data_eps_zero()
2009 	scratch |= DEFECT7374_FSM_WAITING_FOR_CONTROL_READ;  in defect7374_enable_data_eps_zero()
2010 	set_idx_reg(dev->regs, SCRATCH, scratch);  in defect7374_enable_data_eps_zero()
2698 	u32 scratch, fsmvalue;  in defect7374_workaround()  local
2702 	scratch = get_idx_reg(dev->regs, SCRATCH);  in defect7374_workaround()
2703 	fsmvalue = scratch & (0xf << DEFECT7374_FSM_FIELD);  in defect7374_workaround()
2704 	scratch &= ~(0xf << DEFECT7374_FSM_FIELD);  in defect7374_workaround()
2718 		scratch |= DEFECT7374_FSM_NON_SS_CONTROL_READ;  in defect7374_workaround()
2732 			scratch |= DEFECT7374_FSM_SS_CONTROL_READ;  in defect7374_workaround()
2765 	set_idx_reg(dev->regs, SCRATCH, scratch);  in defect7374_workaround()
3016 	u32			num, scratch;  in handle_stat0_irqs()  local
3113 			scratch = BIT(DATA_PACKET_TRANSMITTED_INTERRUPT) |  in handle_stat0_irqs()
3118 			scratch = BIT(DATA_PACKET_RECEIVED_INTERRUPT) |  in handle_stat0_irqs()
3121 		writel(scratch, &dev->epregs[0].ep_irqenb);  in handle_stat0_irqs()
3248 		scratch = stat & 0x7f;  in handle_stat0_irqs()
3250 		for (num = 0; scratch; num++) {  in handle_stat0_irqs()
3255 			if ((scratch & t) == 0)  in handle_stat0_irqs()
3257 			scratch ^= t;  in handle_stat0_irqs()
3282 	u32			tmp, num, mask, scratch;  in handle_stat1_irqs()  local
3380 	scratch = stat & DMA_INTERRUPTS;  in handle_stat1_irqs()
3382 	scratch >>= 9;  in handle_stat1_irqs()
3383 	for (num = 0; scratch; num++) {  in handle_stat1_irqs()
3387 		if ((tmp & scratch) == 0)  in handle_stat1_irqs()
3389 		scratch ^= tmp;  in handle_stat1_irqs()