Lines Matching refs:BIT
162 #define valid_bit cpu_to_le32(BIT(VALID_BIT))
163 #define dma_done_ie cpu_to_le32(BIT(DMA_DONE_INTERRUPT_ENABLE))
176 tmp |= BIT(ep->num); in enable_pciirqenb()
178 tmp |= BIT(ep_bit[ep->num]); in enable_pciirqenb()
246 writel(BIT(FIFO_FLUSH), &ep->regs->ep_stat); in net2280_enable()
267 writel(BIT(CLEAR_NAK_OUT_PACKETS_MODE), in net2280_enable()
286 tmp |= BIT(ENDPOINT_ENABLE); in net2280_enable()
292 tmp |= BIT(IN_ENDPOINT_ENABLE); in net2280_enable()
295 tmp |= BIT(OUT_ENDPOINT_ENABLE); in net2280_enable()
310 writel(BIT(SET_NAK_OUT_PACKETS), &ep->regs->ep_rsp); in net2280_enable()
315 writel(BIT(CLEAR_NAK_OUT_PACKETS) | in net2280_enable()
316 BIT(CLEAR_NAK_OUT_PACKETS_MODE), &ep->regs->ep_rsp); in net2280_enable()
327 tmp = BIT(DATA_PACKET_RECEIVED_INTERRUPT_ENABLE) | in net2280_enable()
328 BIT(DATA_PACKET_TRANSMITTED_INTERRUPT_ENABLE); in net2280_enable()
333 tmp = BIT((8 + ep->num)); /* completion */ in net2280_enable()
342 tmp = BIT(SHORT_PACKET_TRANSFERRED_INTERRUPT_ENABLE); in net2280_enable()
397 writel(BIT(DMA_SCATTER_GATHER_DONE_INTERRUPT) | in ep_reset_228x()
398 BIT(DMA_TRANSACTION_DONE_INTERRUPT) | in ep_reset_228x()
399 BIT(DMA_ABORT), in ep_reset_228x()
403 tmp &= ~BIT(ep->num); in ep_reset_228x()
407 tmp &= ~BIT((8 + ep->num)); /* completion */ in ep_reset_228x()
416 tmp = BIT(SET_NAK_OUT_PACKETS_MODE) | in ep_reset_228x()
417 BIT(SET_NAK_OUT_PACKETS) | in ep_reset_228x()
418 BIT(CLEAR_EP_HIDE_STATUS_PHASE) | in ep_reset_228x()
419 BIT(CLEAR_INTERRUPT_MODE); in ep_reset_228x()
422 tmp = BIT(CLEAR_NAK_OUT_PACKETS_MODE) | in ep_reset_228x()
423 BIT(CLEAR_NAK_OUT_PACKETS) | in ep_reset_228x()
424 BIT(CLEAR_EP_HIDE_STATUS_PHASE) | in ep_reset_228x()
425 BIT(CLEAR_INTERRUPT_MODE); in ep_reset_228x()
429 tmp |= BIT(CLEAR_ENDPOINT_TOGGLE) | in ep_reset_228x()
430 BIT(CLEAR_ENDPOINT_HALT); in ep_reset_228x()
436 tmp = BIT(FIFO_OVERFLOW) | in ep_reset_228x()
437 BIT(FIFO_UNDERFLOW); in ep_reset_228x()
441 writel(tmp | BIT(TIMEOUT) | in ep_reset_228x()
442 BIT(USB_STALL_SENT) | in ep_reset_228x()
443 BIT(USB_IN_NAK_SENT) | in ep_reset_228x()
444 BIT(USB_IN_ACK_RCVD) | in ep_reset_228x()
445 BIT(USB_OUT_PING_NAK_SENT) | in ep_reset_228x()
446 BIT(USB_OUT_ACK_SENT) | in ep_reset_228x()
447 BIT(FIFO_FLUSH) | in ep_reset_228x()
448 BIT(SHORT_PACKET_OUT_DONE_INTERRUPT) | in ep_reset_228x()
449 BIT(SHORT_PACKET_TRANSFERRED_INTERRUPT) | in ep_reset_228x()
450 BIT(DATA_PACKET_RECEIVED_INTERRUPT) | in ep_reset_228x()
451 BIT(DATA_PACKET_TRANSMITTED_INTERRUPT) | in ep_reset_228x()
452 BIT(DATA_OUT_PING_TOKEN_INTERRUPT) | in ep_reset_228x()
453 BIT(DATA_IN_TOKEN_INTERRUPT), in ep_reset_228x()
473 writel(BIT(DMA_ABORT_DONE_INTERRUPT) | in ep_reset_338x()
474 BIT(DMA_PAUSE_DONE_INTERRUPT) | in ep_reset_338x()
475 BIT(DMA_SCATTER_GATHER_DONE_INTERRUPT) | in ep_reset_338x()
476 BIT(DMA_TRANSACTION_DONE_INTERRUPT), in ep_reset_338x()
488 tmp &= ~BIT(ep_bit[ep->num]); in ep_reset_338x()
493 tmp &= ~BIT((8 + ep->num)); /* completion */ in ep_reset_338x()
499 writel(BIT(SHORT_PACKET_OUT_DONE_INTERRUPT) | in ep_reset_338x()
500 BIT(SHORT_PACKET_TRANSFERRED_INTERRUPT) | in ep_reset_338x()
501 BIT(FIFO_OVERFLOW) | in ep_reset_338x()
502 BIT(DATA_PACKET_RECEIVED_INTERRUPT) | in ep_reset_338x()
503 BIT(DATA_PACKET_TRANSMITTED_INTERRUPT) | in ep_reset_338x()
504 BIT(DATA_OUT_PING_TOKEN_INTERRUPT) | in ep_reset_338x()
505 BIT(DATA_IN_TOKEN_INTERRUPT), &ep->regs->ep_stat); in ep_reset_338x()
681 if (tmp & BIT(NAK_OUT_PACKETS)) { in out_flush()
684 writel(BIT(SET_NAK_OUT_PACKETS), &ep->regs->ep_rsp); in out_flush()
687 writel(BIT(DATA_OUT_PING_TOKEN_INTERRUPT) | in out_flush()
688 BIT(DATA_PACKET_RECEIVED_INTERRUPT), in out_flush()
690 writel(BIT(FIFO_FLUSH), statp); in out_flush()
694 if (tmp & BIT(DATA_OUT_PING_TOKEN_INTERRUPT) && in out_flush()
700 handshake(statp, BIT(USB_OUT_PING_NAK_SENT), in out_flush()
701 BIT(USB_OUT_PING_NAK_SENT), usec); in out_flush()
727 if ((tmp & BIT(NAK_OUT_PACKETS))) in read_fifo()
729 else if ((tmp & BIT(FIFO_FULL))) { in read_fifo()
746 if (count == 0 && (tmp & BIT(NAK_OUT_PACKETS)) == 0) in read_fifo()
792 writel(BIT(CLEAR_NAK_OUT_PACKETS), &ep->regs->ep_rsp); in read_fifo()
813 dmacount |= BIT(DMA_DIRECTION); in fill_dma_desc()
816 dmacount |= BIT(END_OF_CHAIN); in fill_dma_desc()
820 dmacount |= BIT(VALID_BIT); in fill_dma_desc()
821 dmacount |= BIT(DMA_DONE_INTERRUPT_ENABLE); in fill_dma_desc()
832 BIT(DMA_SCATTER_GATHER_DONE_INTERRUPT) |
833 BIT(DMA_CLEAR_COUNT_ENABLE) |
836 BIT(DMA_VALID_BIT_POLLING_ENABLE) |
837 BIT(DMA_VALID_BIT_ENABLE) |
838 BIT(DMA_SCATTER_GATHER_ENABLE) |
840 BIT(DMA_ENABLE);
844 handshake(&dma->dmactl, BIT(DMA_ENABLE), 0, 50); in spin_stop_dma()
849 writel(readl(&dma->dmactl) & ~BIT(DMA_ENABLE), &dma->dmactl); in stop_dma()
856 unsigned int tmp = BIT(VALID_BIT) | (ep->is_in << DMA_DIRECTION); in start_queue()
859 tmp |= BIT(END_OF_CHAIN); in start_queue()
866 dmactl |= BIT(DMA_REQUEST_OUTSTANDING); in start_queue()
872 writel(BIT(DMA_START), &dma->dmastat); in start_queue()
886 WARN_ON(readl(&dma->dmactl) & BIT(DMA_ENABLE)); in start_dma()
891 BIT(NAK_OUT_PACKETS))) { in start_dma()
892 writel(BIT(SHORT_PACKET_TRANSFERRED_INTERRUPT), in start_dma()
905 writel(BIT(DMA_DONE_INTERRUPT_ENABLE) | tmp, in start_dma()
910 writel(BIT(DMA_ENABLE), &dma->dmactl); in start_dma()
911 writel(BIT(DMA_START), &dma->dmastat); in start_dma()
925 tmp |= BIT(DMA_FIFO_VALIDATE); in start_dma()
935 req->td->dmacount |= cpu_to_le32(BIT(END_OF_CHAIN)); in start_dma()
1050 (readl(&ep->regs->ep_rsp) & BIT(CLEAR_ENDPOINT_HALT)))) { in net2280_queue()
1072 if ((s & BIT(FIFO_EMPTY)) == 0) { in net2280_queue()
1094 if (req && (s & BIT(NAK_OUT_PACKETS))) in net2280_queue()
1095 writel(BIT(CLEAR_NAK_OUT_PACKETS), in net2280_queue()
1155 if ((tmp & BIT(VALID_BIT)) != 0) in scan_dma_completions()
1179 if ((tmp & BIT(NAK_OUT_PACKETS)) == 0) { in scan_dma_completions()
1216 writel(BIT(DMA_ABORT), &ep->dma->dmastat); in abort_dma()
1419 avail = readl(&ep->regs->ep_avail) & (BIT(12) - 1); in net2280_fifo_status()
1445 writel(BIT(FIFO_FLUSH), &ep->regs->ep_stat); in net2280_fifo_flush()
1494 if (tmp & BIT(DEVICE_REMOTE_WAKEUP_ENABLE)) in net2280_wakeup()
1495 writel(BIT(GENERATE_RESUME), &dev->usb->usbstat); in net2280_wakeup()
1515 tmp |= BIT(SELF_POWERED_STATUS); in net2280_set_selfpowered()
1518 tmp &= ~BIT(SELF_POWERED_STATUS); in net2280_set_selfpowered()
1542 writel(tmp | BIT(USB_DETECT_ENABLE), &dev->usb->usbctl); in net2280_pullup()
1544 writel(tmp & ~BIT(USB_DETECT_ENABLE), &dev->usb->usbctl); in net2280_pullup()
1657 if (t1 & BIT(VBUS_PIN)) { in registers_show()
1658 if (t2 & BIT(HIGH_SPEED)) in registers_show()
1693 (t2 & BIT(CLEAR_NAK_OUT_PACKETS)) in registers_show()
1695 (t2 & BIT(CLEAR_EP_HIDE_STATUS_PHASE)) in registers_show()
1697 (t2 & BIT(CLEAR_EP_FORCE_CRC_ERROR)) in registers_show()
1699 (t2 & BIT(CLEAR_INTERRUPT_MODE)) in registers_show()
1701 (t2 & BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE)) in registers_show()
1703 (t2 & BIT(CLEAR_NAK_OUT_PACKETS_MODE)) in registers_show()
1705 (t2 & BIT(CLEAR_ENDPOINT_TOGGLE)) in registers_show()
1707 (t2 & BIT(CLEAR_ENDPOINT_HALT)) in registers_show()
1934 tmp_reg &= ~BIT(NON_CTRL_IN_TOLERATE_BAD_DIR); in defect7374_disable_data_eps()
1937 tmp_reg |= BIT(EP_INITIALIZED); in defect7374_disable_data_eps()
1960 tmp = ((0 << ENDPOINT_NUMBER) | BIT(ENDPOINT_DIRECTION) | in defect7374_enable_data_eps_zero()
1963 BIT(OUT_ENDPOINT_ENABLE) | BIT(IN_ENDPOINT_ENABLE) : in defect7374_enable_data_eps_zero()
1964 BIT(ENDPOINT_ENABLE))); in defect7374_enable_data_eps_zero()
1970 tmp = ((0 << ENDPOINT_NUMBER) | BIT(ENDPOINT_ENABLE)); in defect7374_enable_data_eps_zero()
1987 BIT(CLEAR_ACK_ERROR_CODE) | 0); in defect7374_enable_data_eps_zero()
1997 BIT(NON_CTRL_IN_TOLERATE_BAD_DIR) | 0); in defect7374_enable_data_eps_zero()
2001 ~BIT(EP_INITIALIZED); in defect7374_enable_data_eps_zero()
2045 writel(~(u32)BIT(SUSPEND_REQUEST_INTERRUPT), &dev->regs->irqstat1), in usb_reset_228x()
2049 BIT(PCI_ENABLE) | in usb_reset_228x()
2050 BIT(FIFO_SOFT_RESET) | in usb_reset_228x()
2051 BIT(USB_SOFT_RESET) | in usb_reset_228x()
2052 BIT(M8051_RESET); in usb_reset_228x()
2084 writel(BIT(DMA_ABORT), &dma->dmastat); in usb_reset_338x()
2094 BIT(PCI_ENABLE) | in usb_reset_338x()
2095 BIT(FIFO_SOFT_RESET) | in usb_reset_338x()
2096 BIT(USB_SOFT_RESET) | in usb_reset_338x()
2097 BIT(M8051_RESET); in usb_reset_338x()
2204 ~(BIT(U1_ENABLE) | BIT(U2_ENABLE) | BIT(LTM_ENABLE)); in usb_reinit_338x()
2243 val |= BIT(RECOVERY_IDLE_TO_RECOVER_FMW); in usb_reinit_338x()
2266 writel(BIT(CLEAR_EP_HIDE_STATUS_PHASE) | in ep0_start_228x()
2267 BIT(CLEAR_NAK_OUT_PACKETS) | in ep0_start_228x()
2268 BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE), in ep0_start_228x()
2277 writel(BIT(SET_TEST_MODE) | in ep0_start_228x()
2278 BIT(SET_ADDRESS) | in ep0_start_228x()
2279 BIT(DEVICE_SET_CLEAR_DEVICE_REMOTE_WAKEUP) | in ep0_start_228x()
2280 BIT(GET_DEVICE_STATUS) | in ep0_start_228x()
2281 BIT(GET_INTERFACE_STATUS), in ep0_start_228x()
2283 writel(BIT(USB_ROOT_PORT_WAKEUP_ENABLE) | in ep0_start_228x()
2284 BIT(SELF_POWERED_USB_DEVICE) | in ep0_start_228x()
2285 BIT(REMOTE_WAKEUP_SUPPORT) | in ep0_start_228x()
2287 BIT(SELF_POWERED_STATUS), in ep0_start_228x()
2291 writel(BIT(SETUP_PACKET_INTERRUPT_ENABLE) | in ep0_start_228x()
2292 BIT(ENDPOINT_0_INTERRUPT_ENABLE), in ep0_start_228x()
2294 writel(BIT(PCI_INTERRUPT_ENABLE) | in ep0_start_228x()
2295 BIT(PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE) | in ep0_start_228x()
2296 BIT(PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE) | in ep0_start_228x()
2297 BIT(PCI_RETRY_ABORT_INTERRUPT_ENABLE) | in ep0_start_228x()
2298 BIT(VBUS_INTERRUPT_ENABLE) | in ep0_start_228x()
2299 BIT(ROOT_PORT_RESET_INTERRUPT_ENABLE) | in ep0_start_228x()
2300 BIT(SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE), in ep0_start_228x()
2311 writel(BIT(CLEAR_NAK_OUT_PACKETS_MODE) | in ep0_start_338x()
2312 BIT(SET_EP_HIDE_STATUS_PHASE), in ep0_start_338x()
2321 writel(BIT(SET_ISOCHRONOUS_DELAY) | in ep0_start_338x()
2322 BIT(SET_SEL) | in ep0_start_338x()
2323 BIT(SET_TEST_MODE) | in ep0_start_338x()
2324 BIT(SET_ADDRESS) | in ep0_start_338x()
2325 BIT(GET_INTERFACE_STATUS) | in ep0_start_338x()
2326 BIT(GET_DEVICE_STATUS), in ep0_start_338x()
2329 writel(BIT(USB_ROOT_PORT_WAKEUP_ENABLE) | in ep0_start_338x()
2331 BIT(DEVICE_REMOTE_WAKEUP_ENABLE), in ep0_start_338x()
2335 writel(BIT(SETUP_PACKET_INTERRUPT_ENABLE) | in ep0_start_338x()
2336 BIT(ENDPOINT_0_INTERRUPT_ENABLE), in ep0_start_338x()
2338 writel(BIT(PCI_INTERRUPT_ENABLE) | in ep0_start_338x()
2339 BIT(ROOT_PORT_RESET_INTERRUPT_ENABLE) | in ep0_start_338x()
2340 BIT(SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE) | in ep0_start_338x()
2341 BIT(VBUS_INTERRUPT_ENABLE), in ep0_start_338x()
2485 writel(t & ~BIT(NAK_OUT_PACKETS), &ep->regs->ep_stat); in handle_ep_small()
2503 if (t & BIT(DATA_OUT_PING_TOKEN_INTERRUPT)) { in handle_ep_small()
2512 } else if (t & BIT(DATA_IN_TOKEN_INTERRUPT)) { in handle_ep_small()
2523 if (t & BIT(DATA_IN_TOKEN_INTERRUPT)) { in handle_ep_small()
2530 } else if (((t & BIT(DATA_OUT_PING_TOKEN_INTERRUPT)) && in handle_ep_small()
2549 if (t & BIT(SHORT_PACKET_TRANSFERRED_INTERRUPT)) { in handle_ep_small()
2575 if (likely(t & BIT(FIFO_EMPTY))) { in handle_ep_small()
2587 writel(BIT(DMA_ABORT), &ep->dma->dmastat); in handle_ep_small()
2617 } else if (t & BIT(DATA_PACKET_RECEIVED_INTERRUPT)) { in handle_ep_small()
2622 } else if (t & BIT(DATA_PACKET_TRANSMITTED_INTERRUPT)) { in handle_ep_small()
2671 if (t & BIT(DATA_PACKET_TRANSMITTED_INTERRUPT)) in handle_ep_small()
2711 if (!(readl(&dev->usb->usbstat) & BIT(SUPER_SPEED_MODE))) { in defect7374_workaround()
2779 val |= BIT(SEQUENCE_NUMBER_RESET); in ep_clear_seqnum()
2807 status |= BIT(0); in handle_stat0_irqs_superspeed()
2821 BIT(CLEAR_ENDPOINT_HALT); in handle_stat0_irqs_superspeed()
2841 ~BIT(U1_ENABLE), in handle_stat0_irqs_superspeed()
2849 ~BIT(U2_ENABLE), in handle_stat0_irqs_superspeed()
2857 ~BIT(LTM_ENABLE), in handle_stat0_irqs_superspeed()
2869 ~BIT(DEVICE_REMOTE_WAKEUP_ENABLE), in handle_stat0_irqs_superspeed()
2907 BIT(U1_ENABLE), in handle_stat0_irqs_superspeed()
2915 BIT(U2_ENABLE), in handle_stat0_irqs_superspeed()
2923 BIT(LTM_ENABLE), in handle_stat0_irqs_superspeed()
2935 BIT(DEVICE_REMOTE_WAKEUP_ENABLE), in handle_stat0_irqs_superspeed()
2999 bit = BIT(ep_bit[index]); in usb338x_handle_ep_intr()
3019 stat &= ~BIT(INTA_ASSERTED); in handle_stat0_irqs()
3025 if (unlikely(stat & BIT(SETUP_PACKET_INTERRUPT))) { in handle_stat0_irqs()
3035 if (val & BIT(SUPER_SPEED)) { in handle_stat0_irqs()
3039 } else if (val & BIT(HIGH_SPEED)) { in handle_stat0_irqs()
3057 stat &= ~BIT(ENDPOINT_0_INTERRUPT); in handle_stat0_irqs()
3068 tmp = BIT(FIFO_OVERFLOW) | in handle_stat0_irqs()
3069 BIT(FIFO_UNDERFLOW); in handle_stat0_irqs()
3073 writel(tmp | BIT(TIMEOUT) | in handle_stat0_irqs()
3074 BIT(USB_STALL_SENT) | in handle_stat0_irqs()
3075 BIT(USB_IN_NAK_SENT) | in handle_stat0_irqs()
3076 BIT(USB_IN_ACK_RCVD) | in handle_stat0_irqs()
3077 BIT(USB_OUT_PING_NAK_SENT) | in handle_stat0_irqs()
3078 BIT(USB_OUT_ACK_SENT) | in handle_stat0_irqs()
3079 BIT(SHORT_PACKET_OUT_DONE_INTERRUPT) | in handle_stat0_irqs()
3080 BIT(SHORT_PACKET_TRANSFERRED_INTERRUPT) | in handle_stat0_irqs()
3081 BIT(DATA_PACKET_RECEIVED_INTERRUPT) | in handle_stat0_irqs()
3082 BIT(DATA_PACKET_TRANSMITTED_INTERRUPT) | in handle_stat0_irqs()
3083 BIT(DATA_OUT_PING_TOKEN_INTERRUPT) | in handle_stat0_irqs()
3084 BIT(DATA_IN_TOKEN_INTERRUPT), in handle_stat0_irqs()
3103 writel(BIT(SETUP_PACKET_INTERRUPT), &dev->regs->irqstat0); in handle_stat0_irqs()
3104 stat ^= BIT(SETUP_PACKET_INTERRUPT); in handle_stat0_irqs()
3113 scratch = BIT(DATA_PACKET_TRANSMITTED_INTERRUPT) | in handle_stat0_irqs()
3114 BIT(DATA_OUT_PING_TOKEN_INTERRUPT) | in handle_stat0_irqs()
3115 BIT(DATA_IN_TOKEN_INTERRUPT); in handle_stat0_irqs()
3118 scratch = BIT(DATA_PACKET_RECEIVED_INTERRUPT) | in handle_stat0_irqs()
3119 BIT(DATA_OUT_PING_TOKEN_INTERRUPT) | in handle_stat0_irqs()
3120 BIT(DATA_IN_TOKEN_INTERRUPT); in handle_stat0_irqs()
3145 if (readl(&e->regs->ep_rsp) & BIT(SET_ENDPOINT_HALT)) in handle_stat0_irqs()
3238 u32 mask = (BIT(ENDPOINT_0_INTERRUPT) | in handle_stat0_irqs()
3254 t = BIT(num); in handle_stat0_irqs()
3268 #define DMA_INTERRUPTS (BIT(DMA_D_INTERRUPT) | \
3269 BIT(DMA_C_INTERRUPT) | \
3270 BIT(DMA_B_INTERRUPT) | \
3271 BIT(DMA_A_INTERRUPT))
3273 BIT(PCI_MASTER_ABORT_RECEIVED_INTERRUPT) | \
3274 BIT(PCI_TARGET_ABORT_RECEIVED_INTERRUPT) | \
3275 BIT(PCI_RETRY_ABORT_INTERRUPT))
3285 tmp = BIT(VBUS_INTERRUPT) | BIT(ROOT_PORT_RESET_INTERRUPT); in handle_stat1_irqs()
3286 mask = BIT(SUPER_SPEED) | BIT(HIGH_SPEED) | BIT(FULL_SPEED); in handle_stat1_irqs()
3303 if ((stat & BIT(VBUS_INTERRUPT)) && in handle_stat1_irqs()
3305 BIT(VBUS_PIN)) == 0) { in handle_stat1_irqs()
3309 } else if ((stat & BIT(ROOT_PORT_RESET_INTERRUPT)) && in handle_stat1_irqs()
3343 tmp = BIT(SUSPEND_REQUEST_CHANGE_INTERRUPT); in handle_stat1_irqs()
3346 if (stat & BIT(SUSPEND_REQUEST_INTERRUPT)) { in handle_stat1_irqs()
3350 stat &= ~BIT(SUSPEND_REQUEST_INTERRUPT); in handle_stat1_irqs()
3365 stat &= ~(BIT(CONTROL_STATUS_INTERRUPT) | in handle_stat1_irqs()
3366 BIT(SUSPEND_REQUEST_INTERRUPT) | in handle_stat1_irqs()
3367 BIT(RESUME_INTERRUPT) | in handle_stat1_irqs()
3368 BIT(SOF_INTERRUPT)); in handle_stat1_irqs()
3370 stat &= ~(BIT(CONTROL_STATUS_INTERRUPT) | in handle_stat1_irqs()
3371 BIT(RESUME_INTERRUPT) | in handle_stat1_irqs()
3372 BIT(SOF_DOWN_INTERRUPT) | in handle_stat1_irqs()
3373 BIT(SOF_INTERRUPT)); in handle_stat1_irqs()
3386 tmp = BIT(num); in handle_stat1_irqs()
3405 (tmp & BIT(DMA_TRANSACTION_DONE_INTERRUPT))) in handle_stat1_irqs()
3409 if (!(tmp & BIT(DMA_TRANSACTION_DONE_INTERRUPT))) { in handle_stat1_irqs()
3460 (!(readl(&dev->regs->irqstat0) & BIT(INTA_ASSERTED)))) in net2280_irq()
3612 dev->enhanced_mode = !!(usbstat & BIT(11)); in net2280_probe()
3680 writel(BIT(DMA_MEMORY_WRITE_AND_INVALIDATE_ENABLE) | in net2280_probe()
3685 BIT(DMA_READ_MULTIPLE_ENABLE) | in net2280_probe()
3686 BIT(DMA_READ_LINE_ENABLE), in net2280_probe()