Lines Matching refs:u32
125 u32 rsvd[5];
126 u32 dboff; /* doorbell register offset */
127 u32 rtsoff; /* runtime register offset */
128 u32 vuoff; /* vendor unique register offset */
133 u32 usbcmd; /* Command register */
134 u32 rsvd1[11];
135 u32 dcbaapl; /* Device Context Base Address low register */
136 u32 dcbaaph; /* Device Context Base Address high register */
137 u32 rsvd2[243];
138 u32 portsc; /* port status and control register*/
139 u32 portlinkinfo; /* port link info register*/
140 u32 rsvd3[9917];
141 u32 doorbell; /* doorbell register */
146 u32 epxoutcr0; /* ep out control 0 register */
147 u32 epxoutcr1; /* ep out control 1 register */
148 u32 epxincr0; /* ep in control 0 register */
149 u32 epxincr1; /* ep in control 1 register */
154 u32 curdeqlo; /* current TRB pointer low */
155 u32 curdeqhi; /* current TRB pointer high */
156 u32 statuslo; /* transfer status low */
157 u32 statushi; /* transfer status high */
162 u32 ctrlepenable; /* control endpoint enable register */
163 u32 setuplock; /* setup lock register */
164 u32 endcomplete; /* endpoint transfer complete register */
165 u32 intrcause; /* interrupt cause register */
166 u32 intrenable; /* interrupt enable register */
167 u32 trbcomplete; /* TRB complete register */
168 u32 linkchange; /* link change register */
169 u32 rsvd1[5];
170 u32 trbunderrun; /* TRB underrun register */
171 u32 rsvd2[43];
172 u32 bridgesetting; /* bridge setting register */
173 u32 rsvd3[7];
176 u32 ltssm; /* LTSSM control register */
177 u32 pipe; /* PIPE control register */
178 u32 linkcr0; /* link control 0 register */
179 u32 linkcr1; /* link control 1 register */
180 u32 rsvd6[60];
181 u32 mib0; /* MIB0 counter register */
182 u32 usblink; /* usb link control register */
183 u32 ltssmstate; /* LTSSM state register */
184 u32 linkerrorcause; /* link error cause register */
185 u32 rsvd7[60];
186 u32 devaddrtiebrkr; /* device address and tie breaker */
187 u32 itpinfo0; /* ITP info 0 register */
188 u32 itpinfo1; /* ITP info 1 register */
189 u32 rsvd8[61];
191 u32 rsvd9[64];
192 u32 phyaddr; /* PHY address register */
193 u32 phydata; /* PHY data register */
198 u32 rsvd0;
199 u32 rsvd1;
200 u32 trb_addr_lo; /* TRB address low 32 bit */
201 u32 trb_addr_hi; /* TRB address high 32 bit */
202 u32 rsvd2;
203 u32 rsvd3;
209 u32 own:1; /* owner of TRB */
210 u32 rsvd1:3;
211 u32 chain:1; /* associate this TRB with the
213 u32 ioc:1; /* interrupt on complete */
214 u32 rsvd2:4;
215 u32 type:6; /* TRB type */
219 u32 dir:1; /* Working at data stage of control endpoint
221 u32 rsvd3:15;
228 u32 buf_addr_lo; /* data buffer address low 32 bit */
229 u32 buf_addr_hi; /* data buffer address high 32 bit */
230 u32 trb_len; /* transfer length */
296 u32 direction;
298 u32 processing; /* there is ep request