56 #define gr_read32(x) (ioread32be((x)))  macro
131 	u32 epctrl = gr_read32(&ep->regs->epctrl);  in gr_seq_ep_show()
132 	u32 epstat = gr_read32(&ep->regs->epstat);  in gr_seq_ep_show()
190 	u32 control = gr_read32(&dev->regs->control);  in gr_seq_show()
191 	u32 status = gr_read32(&dev->regs->status);  in gr_seq_show()
415 	dmactrl = gr_read32(&ep->regs->dmactrl);  in gr_start_dma()
446 	dmactrl = gr_read32(&ep->regs->dmactrl);  in gr_abort_dma()
711 	epctrl = gr_read32(&dev->epo[0].regs->epctrl);  in gr_control_stall()
713 	epctrl = gr_read32(&dev->epi[0].regs->epctrl);  in gr_control_stall()
749 	epctrl = gr_read32(&ep->regs->epctrl);  in gr_ep_halt_wedge()
823 	control = gr_read32(&dev->regs->control);  in gr_ep0_testmode_complete()
895 	control = gr_read32(&dev->regs->control) & ~GR_CONTROL_UA_MASK;  in gr_set_address()
1018 		halted = gr_read32(&ep->regs->epctrl) & GR_EPCTRL_EH;  in gr_endpoint_request()
1212 	status = gr_read32(&dev->regs->status);  in gr_enable_vbus_detect()
1268 	if (gr_read32(&ep->regs->epstat) & (GR_EPSTAT_B1 | GR_EPSTAT_B0))  in gr_handle_in_ep()
1324 		ep_dmactrl = gr_read32(&ep->regs->dmactrl);  in gr_handle_out_ep()
1338 	u32 status = gr_read32(&dev->regs->status);  in gr_handle_state_changes()
1456 			if (gr_read32(&ep->regs->dmactrl) & GR_DMACTRL_AE) {  in gr_irq_handler()
1511 	epctrl = gr_read32(&ep->regs->epctrl);  in gr_ep_enable()
1814 	epstat = gr_read32(&ep->regs->epstat);  in gr_fifo_status()
1838 	epctrl = gr_read32(&ep->regs->epctrl);  in gr_fifo_flush()
1871 	return gr_read32(&dev->regs->status) & GR_STATUS_FN_MASK;  in gr_get_frame()
1889 		   gr_read32(&dev->regs->control) | GR_CONTROL_RW);  in gr_wakeup()
1907 	control = gr_read32(&dev->regs->control);  in gr_pullup()
2185 	status = gr_read32(&dev->regs->status);  in gr_probe()