65 #define GR_BUFFER_SIZE(epctrl)					      \  argument
66 	((((epctrl) & GR_EPCTRL_BUFSZ_MASK) >> GR_EPCTRL_BUFSZ_POS) * \
131 	u32 epctrl = gr_read32(&ep->regs->epctrl);  in gr_seq_ep_show()  local
133 	int mode = (epctrl & GR_EPCTRL_TT_MASK) >> GR_EPCTRL_TT_POS;  in gr_seq_ep_show()
138 	seq_printf(seq, "  halted: %d\n", !!(epctrl & GR_EPCTRL_EH));  in gr_seq_ep_show()
139 	seq_printf(seq, "  disabled: %d\n", !!(epctrl & GR_EPCTRL_ED));  in gr_seq_ep_show()
140 	seq_printf(seq, "  valid: %d\n", !!(epctrl & GR_EPCTRL_EV));  in gr_seq_ep_show()
150 			   (epctrl & GR_EPCTRL_NT_MASK) >> GR_EPCTRL_NT_POS);  in gr_seq_ep_show()
693 	gr_write32(&ep->regs->epctrl, 0);  in gr_ep_reset()
709 	u32 epctrl;  in gr_control_stall()  local
711 	epctrl = gr_read32(&dev->epo[0].regs->epctrl);  in gr_control_stall()
712 	gr_write32(&dev->epo[0].regs->epctrl, epctrl | GR_EPCTRL_CS);  in gr_control_stall()
713 	epctrl = gr_read32(&dev->epi[0].regs->epctrl);  in gr_control_stall()
714 	gr_write32(&dev->epi[0].regs->epctrl, epctrl | GR_EPCTRL_CS);  in gr_control_stall()
726 	u32 epctrl;  in gr_ep_halt_wedge()  local
749 	epctrl = gr_read32(&ep->regs->epctrl);  in gr_ep_halt_wedge()
752 		gr_write32(&ep->regs->epctrl, epctrl | GR_EPCTRL_EH);  in gr_ep_halt_wedge()
757 		gr_write32(&ep->regs->epctrl, epctrl & ~GR_EPCTRL_EH);  in gr_ep_halt_wedge()
1018 		halted = gr_read32(&ep->regs->epctrl) & GR_EPCTRL_EH;  in gr_endpoint_request()
1495 	u32 epctrl;  in gr_ep_enable()  local
1511 	epctrl = gr_read32(&ep->regs->epctrl);  in gr_ep_enable()
1512 	if (epctrl & GR_EPCTRL_EV)  in gr_ep_enable()
1544 	buffer_size = GR_BUFFER_SIZE(epctrl);  in gr_ep_enable()
1602 	epctrl = (max << GR_EPCTRL_MAXPL_POS)  in gr_ep_enable()
1607 		epctrl |= GR_EPCTRL_PI;  in gr_ep_enable()
1608 	gr_write32(&ep->regs->epctrl, epctrl);  in gr_ep_enable()
1829 	u32 epctrl;  in gr_fifo_flush()  local
1838 	epctrl = gr_read32(&ep->regs->epctrl);  in gr_fifo_flush()
1839 	epctrl |= GR_EPCTRL_CB;  in gr_fifo_flush()
1840 	gr_write32(&ep->regs->epctrl, epctrl);  in gr_fifo_flush()
2087 	gr_write32(&dev->epo[0].regs->epctrl, epctrl_val);  in gr_udc_init()
2088 	gr_write32(&dev->epi[0].regs->epctrl, epctrl_val | GR_EPCTRL_PI);  in gr_udc_init()