Lines Matching refs:u32
29 u32 hcsparams; /* Host Controller Structural Parameters */
30 u32 hccparams; /* Host Controller Capability Parameters */
32 u32 dciversion; /* Device Controller Interface Version */
33 u32 dccparams; /* Device Controller Capability Parameters */
36 u32 usbcmd; /* USB Command Register */
37 u32 usbsts; /* USB Status Register */
38 u32 usbintr; /* USB Interrupt Enable Register */
39 u32 frindex; /* Frame Index Register */
41 u32 deviceaddr; /* Device Address */
42 u32 endpointlistaddr; /* Endpoint List Address Register */
44 u32 burstsize; /* Master Interface Data Burst Size Register */
45 u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */
47 u32 configflag; /* Configure Flag Register */
48 u32 portsc1; /* Port 1 Status and Control Register */
50 u32 otgsc; /* On-The-Go Status and Control */
51 u32 usbmode; /* USB Mode Register */
52 u32 endptsetupstat; /* Endpoint Setup Status Register */
53 u32 endpointprime; /* Endpoint Initialization Register */
54 u32 endptflush; /* Endpoint Flush Register */
55 u32 endptstatus; /* Endpoint Status Register */
56 u32 endptcomplete; /* Endpoint Complete Register */
57 u32 endptctrl[6]; /* Endpoint Control Registers */
66 u32 hcsparams; /* Host Controller Structural Parameters */
67 u32 hccparams; /* Host Controller Capability Parameters */
69 u32 dciversion; /* Device Controller Interface Version */
70 u32 dccparams; /* Device Controller Capability Parameters */
73 u32 usbcmd; /* USB Command Register */
74 u32 usbsts; /* USB Status Register */
75 u32 usbintr; /* USB Interrupt Enable Register */
76 u32 frindex; /* Frame Index Register */
78 u32 periodiclistbase; /* Periodic Frame List Base Address Register */
79 u32 asynclistaddr; /* Current Asynchronous List Address Register */
81 u32 burstsize; /* Master Interface Data Burst Size Register */
82 u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */
84 u32 configflag; /* Configure Flag Register */
85 u32 portsc1; /* Port 1 Status and Control Register */
87 u32 otgsc; /* On-The-Go Status and Control */
88 u32 usbmode; /* USB Mode Register */
89 u32 endptsetupstat; /* Endpoint Setup Status Register */
90 u32 endpointprime; /* Endpoint Initialization Register */
91 u32 endptflush; /* Endpoint Flush Register */
92 u32 endptstatus; /* Endpoint Status Register */
93 u32 endptcomplete; /* Endpoint Complete Register */
94 u32 endptctrl[6]; /* Endpoint Control Registers */
99 u32 snoop1;
100 u32 snoop2;
101 u32 age_cnt_thresh; /* Age Count Threshold Register */
102 u32 pri_ctrl; /* Priority Control Register */
103 u32 si_ctrl; /* System Interface Control Register */
105 u32 control; /* General Purpose Control Register */
371 u32 max_pkt_length; /* Mult(31-30) , Zlt(29) , Max Pkt len
373 u32 curr_dtd_ptr; /* Current dTD Pointer(31-5) */
374 u32 next_dtd_ptr; /* Next dTD Pointer(31-5), T(0) */
375 u32 size_ioc_int_sts; /* Total bytes (30-16), IOC (15),
377 u32 buff_ptr0; /* Buffer pointer Page 0 (31-12) */
378 u32 buff_ptr1; /* Buffer pointer Page 1 (31-12) */
379 u32 buff_ptr2; /* Buffer pointer Page 2 (31-12) */
380 u32 buff_ptr3; /* Buffer pointer Page 3 (31-12) */
381 u32 buff_ptr4; /* Buffer pointer Page 4 (31-12) */
382 u32 res1;
384 u32 res2[4];
406 u32 next_td_ptr; /* Next TD pointer(31-5), T(0) set
408 u32 size_ioc_sts; /* Total bytes (30-16), IOC (15),
410 u32 buff_ptr0; /* Buffer pointer Page 0 */
411 u32 buff_ptr1; /* Buffer pointer Page 1 */
412 u32 buff_ptr2; /* Buffer pointer Page 2 */
413 u32 buff_ptr3; /* Buffer pointer Page 3 */
414 u32 buff_ptr4; /* Buffer pointer Page 4 */
415 u32 res;
503 u32 max_pipes; /* Device max pipes */
504 u32 bus_reset; /* Device is bus resetting */
505 u32 resume_state; /* USB state to resume */
506 u32 usb_state; /* USB current state */
507 u32 ep0_state; /* Endpoint zero state */
508 u32 ep0_dir; /* Endpoint zero direction: can be