Lines Matching refs:ep0_state
185 udc->ep0_state = WAIT_FOR_SETUP; in qe_ep0_stall()
648 udc->ep0_state = WAIT_FOR_SETUP; in qe_ep_init()
803 && (udc->ep0_state == WAIT_FOR_SETUP)) { in ep0_setup_handle()
841 udc->ep0_state = WAIT_FOR_SETUP; in qe_ep0_rx()
1108 if ((ep->epnum == 0) && (udc->ep0_state == DATA_STATE_NEED_ZLP)) in qe_ep_tx()
1255 udc->ep0_state = DATA_STATE_NEED_ZLP; in ep0_prime_status()
1260 udc->ep0_state = WAIT_FOR_OUT_STATUS; in ep0_prime_status()
1272 switch (udc->ep0_state) { in ep0_req_complete()
1282 udc->ep0_state = WAIT_FOR_SETUP; in ep0_req_complete()
1294 udc->ep0_state = WAIT_FOR_SETUP; in ep0_req_complete()
1314 ep->udc->ep0_state = WAIT_FOR_SETUP; in ep0_txcomplete()
1753 udc->ep0_state = DATA_STATE_XMIT; in __qe_ep_queue()
1755 udc->ep0_state = DATA_STATE_RECV; in __qe_ep_queue()
1842 udc->ep0_state = WAIT_FOR_SETUP; in qe_ep_set_halt()
2078 udc->ep0_state = DATA_STATE_XMIT; in setup_received_handle()
2081 udc->ep0_state = DATA_STATE_RECV; in setup_received_handle()
2097 udc->ep0_state = DATA_STATE_NEED_ZLP; in setup_received_handle()
2155 udc->ep0_state = WAIT_FOR_SETUP; in reset_irq()
2303 udc->ep0_state = WAIT_FOR_SETUP; in fsl_qe_start()
2322 udc->ep0_state = WAIT_FOR_SETUP; in fsl_qe_stop()