Lines Matching refs:tmp
272 u32 tmp; in udc_mask_unused_interrupts() local
275 tmp = AMD_BIT(UDC_DEVINT_SVC) | in udc_mask_unused_interrupts()
283 writel(tmp, &dev->regs->irqmsk); in udc_mask_unused_interrupts()
294 u32 tmp; in udc_enable_ep0_interrupts() local
299 tmp = readl(&dev->regs->ep_irqmsk); in udc_enable_ep0_interrupts()
301 tmp &= AMD_UNMASK_BIT(UDC_EPINT_IN_EP0) in udc_enable_ep0_interrupts()
303 writel(tmp, &dev->regs->ep_irqmsk); in udc_enable_ep0_interrupts()
311 u32 tmp; in udc_enable_dev_setup_interrupts() local
316 tmp = readl(&dev->regs->irqmsk); in udc_enable_dev_setup_interrupts()
319 tmp &= AMD_UNMASK_BIT(UDC_DEVINT_SI) in udc_enable_dev_setup_interrupts()
324 writel(tmp, &dev->regs->irqmsk); in udc_enable_dev_setup_interrupts()
333 u32 tmp; in udc_set_txfifo_addr() local
346 tmp = readl(&dev->ep[i].regs->bufin_framenum); in udc_set_txfifo_addr()
347 tmp = AMD_GETBITS(tmp, UDC_EPIN_BUFF_SIZE); in udc_set_txfifo_addr()
348 ep->txfifo += tmp; in udc_set_txfifo_addr()
374 u32 tmp; in udc_ep_enable() local
399 tmp = readl(&dev->ep[ep->num].regs->ctl); in udc_ep_enable()
400 tmp = AMD_ADDBITS(tmp, desc->bmAttributes, UDC_EPCTL_ET); in udc_ep_enable()
401 writel(tmp, &dev->ep[ep->num].regs->ctl); in udc_ep_enable()
405 tmp = readl(&dev->ep[ep->num].regs->bufout_maxpkt); in udc_ep_enable()
406 tmp = AMD_ADDBITS(tmp, maxpacket, UDC_EP_MAX_PKT_SIZE); in udc_ep_enable()
408 writel(tmp, &dev->ep[ep->num].regs->bufout_maxpkt); in udc_ep_enable()
417 tmp = readl(&dev->ep[ep->num].regs->bufin_framenum); in udc_ep_enable()
419 tmp = AMD_ADDBITS( in udc_ep_enable()
420 tmp, in udc_ep_enable()
424 writel(tmp, &dev->ep[ep->num].regs->bufin_framenum); in udc_ep_enable()
430 tmp = readl(&ep->regs->ctl); in udc_ep_enable()
431 tmp |= AMD_BIT(UDC_EPCTL_F); in udc_ep_enable()
432 writel(tmp, &ep->regs->ctl); in udc_ep_enable()
440 tmp = readl(&dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]); in udc_ep_enable()
441 tmp = AMD_ADDBITS(tmp, maxpacket, in udc_ep_enable()
443 writel(tmp, &dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]); in udc_ep_enable()
456 tmp = readl(&dev->csr->ne[udc_csr_epix]); in udc_ep_enable()
458 tmp = AMD_ADDBITS(tmp, maxpacket, UDC_CSR_NE_MAX_PKT); in udc_ep_enable()
460 tmp = AMD_ADDBITS(tmp, desc->bEndpointAddress, UDC_CSR_NE_NUM); in udc_ep_enable()
462 tmp = AMD_ADDBITS(tmp, ep->in, UDC_CSR_NE_DIR); in udc_ep_enable()
464 tmp = AMD_ADDBITS(tmp, desc->bmAttributes, UDC_CSR_NE_TYPE); in udc_ep_enable()
466 tmp = AMD_ADDBITS(tmp, ep->dev->cur_config, UDC_CSR_NE_CFG); in udc_ep_enable()
468 tmp = AMD_ADDBITS(tmp, ep->dev->cur_intf, UDC_CSR_NE_INTF); in udc_ep_enable()
470 tmp = AMD_ADDBITS(tmp, ep->dev->cur_alt, UDC_CSR_NE_ALT); in udc_ep_enable()
472 writel(tmp, &dev->csr->ne[udc_csr_epix]); in udc_ep_enable()
475 tmp = readl(&dev->regs->ep_irqmsk); in udc_ep_enable()
476 tmp &= AMD_UNMASK_BIT(ep->num); in udc_ep_enable()
477 writel(tmp, &dev->regs->ep_irqmsk); in udc_ep_enable()
484 tmp = readl(&ep->regs->ctl); in udc_ep_enable()
485 tmp |= AMD_BIT(UDC_EPCTL_CNAK); in udc_ep_enable()
486 writel(tmp, &ep->regs->ctl); in udc_ep_enable()
490 tmp = desc->bEndpointAddress; in udc_ep_enable()
500 u32 tmp; in ep_init() local
509 tmp = readl(&ep->regs->ctl); in ep_init()
510 tmp |= AMD_BIT(UDC_EPCTL_SNAK); in ep_init()
511 writel(tmp, &ep->regs->ctl); in ep_init()
515 tmp = readl(®s->ep_irqmsk); in ep_init()
516 tmp |= AMD_BIT(ep->num); in ep_init()
517 writel(tmp, ®s->ep_irqmsk); in ep_init()
521 tmp = readl(&ep->regs->ctl); in ep_init()
522 tmp &= AMD_UNMASK_BIT(UDC_EPCTL_P); in ep_init()
523 writel(tmp, &ep->regs->ctl); in ep_init()
525 tmp = readl(&ep->regs->sts); in ep_init()
526 tmp |= AMD_BIT(UDC_EPSTS_IN); in ep_init()
527 writel(tmp, &ep->regs->sts); in ep_init()
530 tmp = readl(&ep->regs->ctl); in ep_init()
531 tmp |= AMD_BIT(UDC_EPCTL_F); in ep_init()
532 writel(tmp, &ep->regs->ctl); in ep_init()
750 u32 tmp; in udc_rxfifo_read_bytes() local
760 tmp = readl(dev->rxfifo); in udc_rxfifo_read_bytes()
762 *(buf + (i<<2) + j) = (u8)(tmp & UDC_BYTE_MASK); in udc_rxfifo_read_bytes()
763 tmp = tmp >> UDC_BITS_PER_BYTE; in udc_rxfifo_read_bytes()
929 u32 tmp; in prep_dma() local
1002 tmp = readl(&ep->regs->ctl); in prep_dma()
1003 tmp |= AMD_BIT(UDC_EPCTL_CNAK); in prep_dma()
1004 writel(tmp, &ep->regs->ctl); in prep_dma()
1088 u32 tmp; in udc_set_rde() local
1097 tmp = readl(&dev->regs->ctl); in udc_set_rde()
1098 tmp |= AMD_BIT(UDC_DEVCTL_RDE); in udc_set_rde()
1099 writel(tmp, &dev->regs->ctl); in udc_set_rde()
1112 u32 tmp; in udc_queue() local
1160 tmp = readl(&dev->regs->ctl); in udc_queue()
1161 tmp |= AMD_BIT(UDC_DEVCTL_CSR_DONE); in udc_queue()
1162 writel(tmp, &dev->regs->ctl); in udc_queue()
1168 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl); in udc_queue()
1169 tmp |= AMD_BIT(UDC_EPCTL_CNAK); in udc_queue()
1170 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl); in udc_queue()
1199 tmp = readl(&dev->regs->ctl); in udc_queue()
1200 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_RDE); in udc_queue()
1201 writel(tmp, &dev->regs->ctl); in udc_queue()
1220 tmp = readl(&ep->regs->ctl); in udc_queue()
1221 tmp |= AMD_BIT(UDC_EPCTL_CNAK); in udc_queue()
1222 writel(tmp, &ep->regs->ctl); in udc_queue()
1229 tmp = readl(&dev->regs->ep_irqmsk); in udc_queue()
1230 tmp &= AMD_UNMASK_BIT(ep->num); in udc_queue()
1231 writel(tmp, &dev->regs->ep_irqmsk); in udc_queue()
1235 tmp = readl(&dev->regs->ep_irqmsk); in udc_queue()
1236 tmp &= AMD_UNMASK_BIT(ep->num); in udc_queue()
1237 writel(tmp, &dev->regs->ep_irqmsk); in udc_queue()
1328 u32 tmp; in udc_dequeue() local
1331 tmp = readl(&udc->regs->ctl); in udc_dequeue()
1332 writel(tmp & AMD_UNMASK_BIT(UDC_DEVCTL_RDE), in udc_dequeue()
1347 writel(tmp, &udc->regs->ctl); in udc_dequeue()
1363 u32 tmp; in udc_set_halt() local
1388 tmp = readl(&ep->regs->ctl); in udc_set_halt()
1389 tmp |= AMD_BIT(UDC_EPCTL_S); in udc_set_halt()
1390 writel(tmp, &ep->regs->ctl); in udc_set_halt()
1407 tmp = readl(&ep->regs->ctl); in udc_set_halt()
1409 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S); in udc_set_halt()
1411 tmp |= AMD_BIT(UDC_EPCTL_CNAK); in udc_set_halt()
1412 writel(tmp, &ep->regs->ctl); in udc_set_halt()
1448 u32 tmp; in udc_remote_wakeup() local
1454 tmp = readl(&dev->regs->ctl); in udc_remote_wakeup()
1455 tmp |= AMD_BIT(UDC_DEVCTL_RES); in udc_remote_wakeup()
1456 writel(tmp, &dev->regs->ctl); in udc_remote_wakeup()
1457 tmp &= AMD_CLEAR_BIT(UDC_DEVCTL_RES); in udc_remote_wakeup()
1458 writel(tmp, &dev->regs->ctl); in udc_remote_wakeup()
1512 u32 tmp; in udc_basic_init() local
1527 tmp = readl(&dev->regs->ctl); in udc_basic_init()
1528 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_RDE); in udc_basic_init()
1529 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_TDE); in udc_basic_init()
1530 writel(tmp, &dev->regs->ctl); in udc_basic_init()
1533 tmp = readl(&dev->regs->cfg); in udc_basic_init()
1534 tmp |= AMD_BIT(UDC_DEVCFG_CSR_PRG); in udc_basic_init()
1536 tmp |= AMD_BIT(UDC_DEVCFG_SP); in udc_basic_init()
1538 tmp |= AMD_BIT(UDC_DEVCFG_RWKP); in udc_basic_init()
1539 writel(tmp, &dev->regs->cfg); in udc_basic_init()
1550 u32 tmp; in startup_registers() local
1564 tmp = readl(&dev->regs->cfg); in startup_registers()
1566 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD); in startup_registers()
1568 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_HS, UDC_DEVCFG_SPD); in startup_registers()
1569 writel(tmp, &dev->regs->cfg); in startup_registers()
1578 u32 tmp; in udc_setup_endpoints() local
1584 tmp = readl(&dev->regs->sts); in udc_setup_endpoints()
1585 tmp = AMD_GETBITS(tmp, UDC_DEVSTS_ENUM_SPEED); in udc_setup_endpoints()
1586 if (tmp == UDC_DEVSTS_ENUM_SPEED_HIGH) in udc_setup_endpoints()
1588 else if (tmp == UDC_DEVSTS_ENUM_SPEED_FULL) in udc_setup_endpoints()
1592 for (tmp = 0; tmp < UDC_EP_NUM; tmp++) { in udc_setup_endpoints()
1593 ep = &dev->ep[tmp]; in udc_setup_endpoints()
1595 ep->ep.name = ep_info[tmp].name; in udc_setup_endpoints()
1596 ep->ep.caps = ep_info[tmp].caps; in udc_setup_endpoints()
1597 ep->num = tmp; in udc_setup_endpoints()
1602 if (tmp < UDC_EPIN_NUM) { in udc_setup_endpoints()
1610 ep->regs = &dev->ep_regs[tmp]; in udc_setup_endpoints()
1628 if (tmp != UDC_EP0IN_IX && tmp != UDC_EP0OUT_IX in udc_setup_endpoints()
1629 && tmp > UDC_EPIN_NUM) { in udc_setup_endpoints()
1631 reg = readl(&dev->ep[tmp].regs->ctl); in udc_setup_endpoints()
1633 writel(reg, &dev->ep[tmp].regs->ctl); in udc_setup_endpoints()
1634 dev->ep[tmp].naking = 1; in udc_setup_endpoints()
1707 u32 tmp; in udc_tasklet_disconnect() local
1718 for (tmp = 0; tmp < UDC_EP_NUM; tmp++) in udc_tasklet_disconnect()
1719 empty_req_queue(&dev->ep[tmp]); in udc_tasklet_disconnect()
1738 tmp = readl(&dev->regs->cfg); in udc_tasklet_disconnect()
1739 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD); in udc_tasklet_disconnect()
1740 writel(tmp, &dev->regs->cfg); in udc_tasklet_disconnect()
1771 u32 tmp; in udc_timer_function() local
1782 tmp = readl(&udc->regs->ctl); in udc_timer_function()
1783 tmp |= AMD_BIT(UDC_DEVCTL_RDE); in udc_timer_function()
1784 writel(tmp, &udc->regs->ctl); in udc_timer_function()
1821 u32 tmp; in udc_handle_halt_state() local
1824 tmp = readl(&ep->regs->ctl); in udc_handle_halt_state()
1826 if (!(tmp & AMD_BIT(UDC_EPCTL_S))) { in udc_handle_halt_state()
1840 tmp |= AMD_BIT(UDC_EPCTL_CNAK); in udc_handle_halt_state()
1841 writel(tmp, &ep->regs->ctl); in udc_handle_halt_state()
1885 u32 tmp; in activate_control_endpoints() local
1890 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl); in activate_control_endpoints()
1891 tmp |= AMD_BIT(UDC_EPCTL_F); in activate_control_endpoints()
1892 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl); in activate_control_endpoints()
1899 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufin_framenum); in activate_control_endpoints()
1901 tmp = AMD_ADDBITS(tmp, UDC_FS_EPIN0_BUFF_SIZE, in activate_control_endpoints()
1904 tmp = AMD_ADDBITS(tmp, UDC_EPIN0_BUFF_SIZE, in activate_control_endpoints()
1906 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufin_framenum); in activate_control_endpoints()
1909 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt); in activate_control_endpoints()
1911 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0IN_MAX_PKT_SIZE, in activate_control_endpoints()
1914 tmp = AMD_ADDBITS(tmp, UDC_EP0IN_MAX_PKT_SIZE, in activate_control_endpoints()
1916 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt); in activate_control_endpoints()
1919 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt); in activate_control_endpoints()
1921 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE, in activate_control_endpoints()
1924 tmp = AMD_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE, in activate_control_endpoints()
1926 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt); in activate_control_endpoints()
1929 tmp = readl(&dev->csr->ne[0]); in activate_control_endpoints()
1931 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE, in activate_control_endpoints()
1934 tmp = AMD_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE, in activate_control_endpoints()
1936 writel(tmp, &dev->csr->ne[0]); in activate_control_endpoints()
1955 tmp = readl(&dev->regs->ctl); in activate_control_endpoints()
1956 tmp |= AMD_BIT(UDC_DEVCTL_MODE) in activate_control_endpoints()
1960 tmp |= AMD_BIT(UDC_DEVCTL_BF); in activate_control_endpoints()
1962 tmp |= AMD_BIT(UDC_DEVCTL_DU); in activate_control_endpoints()
1963 writel(tmp, &dev->regs->ctl); in activate_control_endpoints()
1967 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl); in activate_control_endpoints()
1968 tmp |= AMD_BIT(UDC_EPCTL_CNAK); in activate_control_endpoints()
1969 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl); in activate_control_endpoints()
1974 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl); in activate_control_endpoints()
1975 tmp |= AMD_BIT(UDC_EPCTL_CNAK); in activate_control_endpoints()
1976 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl); in activate_control_endpoints()
1998 u32 tmp; in amd5536_udc_start() local
2013 tmp = readl(&dev->regs->ctl); in amd5536_udc_start()
2014 tmp = tmp & AMD_CLEAR_BIT(UDC_DEVCTL_SD); in amd5536_udc_start()
2015 writel(tmp, &dev->regs->ctl); in amd5536_udc_start()
2028 int tmp; in shutdown() local
2033 for (tmp = 0; tmp < UDC_EP_NUM; tmp++) in shutdown()
2034 empty_req_queue(&dev->ep[tmp]); in shutdown()
2044 u32 tmp; in amd5536_udc_stop() local
2054 tmp = readl(&dev->regs->ctl); in amd5536_udc_stop()
2055 tmp |= AMD_BIT(UDC_DEVCTL_SD); in amd5536_udc_stop()
2056 writel(tmp, &dev->regs->ctl); in amd5536_udc_stop()
2064 u32 tmp; in udc_process_cnak_queue() local
2069 for (tmp = 0; tmp < UDC_EPIN_NUM_USED; tmp++) { in udc_process_cnak_queue()
2070 if (cnak_pending & (1 << tmp)) { in udc_process_cnak_queue()
2071 DBG(dev, "CNAK pending for ep%d\n", tmp); in udc_process_cnak_queue()
2073 reg = readl(&dev->ep[tmp].regs->ctl); in udc_process_cnak_queue()
2075 writel(reg, &dev->ep[tmp].regs->ctl); in udc_process_cnak_queue()
2076 dev->ep[tmp].naking = 0; in udc_process_cnak_queue()
2077 UDC_QUEUE_CNAK(&dev->ep[tmp], dev->ep[tmp].num); in udc_process_cnak_queue()
2124 u32 tmp; in udc_data_out_isr() local
2134 tmp = readl(&ep->regs->sts); in udc_data_out_isr()
2137 if (tmp & AMD_BIT(UDC_EPSTS_BNA)) { in udc_data_out_isr()
2141 writel(tmp | AMD_BIT(UDC_EPSTS_BNA), &ep->regs->sts); in udc_data_out_isr()
2151 if (tmp & AMD_BIT(UDC_EPSTS_HE)) { in udc_data_out_isr()
2155 writel(tmp | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts); in udc_data_out_isr()
2242 tmp = req->req.length - req->req.actual; in udc_data_out_isr()
2243 if (count > tmp) { in udc_data_out_isr()
2244 if ((tmp % ep->ep.maxpacket) != 0) { in udc_data_out_isr()
2246 ep->ep.name, count, tmp); in udc_data_out_isr()
2249 count = tmp; in udc_data_out_isr()
2338 u32 tmp; in udc_data_in_isr() local
2407 tmp = readl(&dev->regs->ep_irqmsk); in udc_data_in_isr()
2408 tmp |= AMD_BIT(ep->num); in udc_data_in_isr()
2409 writel(tmp, &dev->regs->ep_irqmsk); in udc_data_in_isr()
2470 tmp = readl(&ep->regs->ctl); in udc_data_in_isr()
2471 tmp |= AMD_BIT(UDC_EPCTL_P); in udc_data_in_isr()
2472 writel(tmp, &ep->regs->ctl); in udc_data_in_isr()
2478 tmp = readl( in udc_data_in_isr()
2480 tmp |= AMD_BIT(ep->num); in udc_data_in_isr()
2481 writel(tmp, in udc_data_in_isr()
2499 u32 tmp; in udc_control_out_isr() local
2511 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->sts); in udc_control_out_isr()
2513 if (tmp & AMD_BIT(UDC_EPSTS_BNA)) { in udc_control_out_isr()
2523 tmp = AMD_GETBITS(tmp, UDC_EPSTS_OUT); in udc_control_out_isr()
2524 VDBG(dev, "data_typ = %x\n", tmp); in udc_control_out_isr()
2527 if (tmp == UDC_EPSTS_OUT_SETUP) { in udc_control_out_isr()
2534 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl); in udc_control_out_isr()
2535 tmp |= AMD_BIT(UDC_EPCTL_SNAK); in udc_control_out_isr()
2536 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl); in udc_control_out_isr()
2616 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl); in udc_control_out_isr()
2621 tmp |= AMD_BIT(UDC_EPCTL_CNAK); in udc_control_out_isr()
2622 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl); in udc_control_out_isr()
2628 tmp |= AMD_BIT(UDC_EPCTL_S); in udc_control_out_isr()
2629 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl); in udc_control_out_isr()
2636 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl); in udc_control_out_isr()
2637 tmp |= AMD_BIT(UDC_EPCTL_CNAK); in udc_control_out_isr()
2638 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl); in udc_control_out_isr()
2650 } else if (tmp == UDC_EPSTS_OUT_DATA) { in udc_control_out_isr()
2713 u32 tmp; in udc_control_in_isr() local
2723 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->sts); in udc_control_in_isr()
2725 if (tmp & AMD_BIT(UDC_EPSTS_TDC)) { in udc_control_in_isr()
2734 } else if (tmp & AMD_BIT(UDC_EPSTS_IN)) { in udc_control_in_isr()
2745 tmp = readl(&ep->regs->ctl); in udc_control_in_isr()
2746 tmp |= AMD_BIT(UDC_EPCTL_S); in udc_control_in_isr()
2747 writel(tmp, &ep->regs->ctl); in udc_control_in_isr()
2765 tmp = in udc_control_in_isr()
2767 tmp |= AMD_BIT(UDC_EPCTL_P); in udc_control_in_isr()
2768 writel(tmp, in udc_control_in_isr()
2815 u32 tmp; in udc_dev_isr() local
2826 tmp = readl(&dev->regs->sts); in udc_dev_isr()
2827 cfg = AMD_GETBITS(tmp, UDC_DEVSTS_CFG); in udc_dev_isr()
2852 tmp = readl(&dev->csr->ne[udc_csr_epix]); in udc_dev_isr()
2854 tmp = AMD_ADDBITS(tmp, ep->dev->cur_config, in udc_dev_isr()
2857 writel(tmp, &dev->csr->ne[udc_csr_epix]); in udc_dev_isr()
2861 tmp = readl(&ep->regs->ctl); in udc_dev_isr()
2862 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S); in udc_dev_isr()
2863 writel(tmp, &ep->regs->ctl); in udc_dev_isr()
2867 tmp = dev->driver->setup(&dev->gadget, &setup_data.request); in udc_dev_isr()
2876 tmp = readl(&dev->regs->sts); in udc_dev_isr()
2877 dev->cur_alt = AMD_GETBITS(tmp, UDC_DEVSTS_ALT); in udc_dev_isr()
2878 dev->cur_intf = AMD_GETBITS(tmp, UDC_DEVSTS_INTF); in udc_dev_isr()
2907 tmp = readl(&dev->csr->ne[udc_csr_epix]); in udc_dev_isr()
2909 tmp = AMD_ADDBITS(tmp, ep->dev->cur_intf, in udc_dev_isr()
2913 tmp = AMD_ADDBITS(tmp, ep->dev->cur_alt, in udc_dev_isr()
2916 writel(tmp, &dev->csr->ne[udc_csr_epix]); in udc_dev_isr()
2920 tmp = readl(&ep->regs->ctl); in udc_dev_isr()
2921 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S); in udc_dev_isr()
2922 writel(tmp, &ep->regs->ctl); in udc_dev_isr()
2927 tmp = dev->driver->setup(&dev->gadget, &setup_data.request); in udc_dev_isr()
2958 tmp = readl(&dev->regs->sts); in udc_dev_isr()
2959 if (!(tmp & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY)) in udc_dev_isr()
2971 tmp = readl(&dev->regs->cfg); in udc_dev_isr()
2972 writel(tmp | AMD_BIT(UDC_DEVCFG_DMARST), &dev->regs->cfg); in udc_dev_isr()
2973 writel(tmp, &dev->regs->cfg); in udc_dev_isr()
2982 tmp = readl(&dev->regs->irqmsk); in udc_dev_isr()
2983 tmp &= AMD_UNMASK_BIT(UDC_DEVINT_US); in udc_dev_isr()
2984 writel(tmp, &dev->regs->irqmsk); in udc_dev_isr()
3023 tmp = readl(&dev->regs->sts); in udc_dev_isr()
3024 if (!(tmp & AMD_BIT(UDC_DEVSTS_SESSVLD))) { in udc_dev_isr()
3026 tmp = readl(&dev->regs->irqmsk); in udc_dev_isr()
3027 tmp |= AMD_BIT(UDC_DEVINT_US); in udc_dev_isr()
3028 writel(tmp, &dev->regs->irqmsk); in udc_dev_isr()
3223 char tmp[128]; in udc_probe() local
3243 snprintf(tmp, sizeof(tmp), "%d", dev->irq); in udc_probe()
3246 tmp, dev->phys_addr, dev->chiprev, in udc_probe()
3248 strcpy(tmp, UDC_DRIVER_VERSION_STRING); in udc_probe()
3255 "driver version: %s(for Geode5536 B1)\n", tmp); in udc_probe()