241 	DBG(dev, "dev control    = %08x\n", readl(&dev->regs->ctl));  in print_regs()
359 	if (readl(&ep->regs->ctl) & AMD_BIT(UDC_EPCTL_NAK)) {  in UDC_QUEUE_CNAK()
399 	tmp = readl(&dev->ep[ep->num].regs->ctl);  in udc_ep_enable()
401 	writel(tmp, &dev->ep[ep->num].regs->ctl);  in udc_ep_enable()
430 		tmp = readl(&ep->regs->ctl);  in udc_ep_enable()
432 		writel(tmp, &ep->regs->ctl);  in udc_ep_enable()
484 		tmp = readl(&ep->regs->ctl);  in udc_ep_enable()
486 		writel(tmp, &ep->regs->ctl);  in udc_ep_enable()
509 	tmp = readl(&ep->regs->ctl);  in ep_init()
511 	writel(tmp, &ep->regs->ctl);  in ep_init()
521 		tmp = readl(&ep->regs->ctl);  in ep_init()
523 		writel(tmp, &ep->regs->ctl);  in ep_init()
530 		tmp = readl(&ep->regs->ctl);  in ep_init()
532 		writel(tmp, &ep->regs->ctl);  in ep_init()
1002 				tmp = readl(&ep->regs->ctl);  in prep_dma()
1004 				writel(tmp, &ep->regs->ctl);  in prep_dma()
1097 	tmp = readl(&dev->regs->ctl);  in udc_set_rde()
1099 	writel(tmp, &dev->regs->ctl);  in udc_set_rde()
1160 				tmp = readl(&dev->regs->ctl);  in udc_queue()
1162 				writel(tmp, &dev->regs->ctl);  in udc_queue()
1168 				tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);  in udc_queue()
1170 				writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);  in udc_queue()
1199 				tmp = readl(&dev->regs->ctl);  in udc_queue()
1201 				writel(tmp, &dev->regs->ctl);  in udc_queue()
1220 				tmp = readl(&ep->regs->ctl);  in udc_queue()
1222 				writel(tmp, &ep->regs->ctl);  in udc_queue()
1331 				tmp = readl(&udc->regs->ctl);  in udc_dequeue()
1333 							&udc->regs->ctl);  in udc_dequeue()
1347 				writel(tmp, &udc->regs->ctl);  in udc_dequeue()
1388 			tmp = readl(&ep->regs->ctl);  in udc_set_halt()
1390 			writel(tmp, &ep->regs->ctl);  in udc_set_halt()
1407 			tmp = readl(&ep->regs->ctl);  in udc_set_halt()
1412 			writel(tmp, &ep->regs->ctl);  in udc_set_halt()
1454 	tmp = readl(&dev->regs->ctl);  in udc_remote_wakeup()
1456 	writel(tmp, &dev->regs->ctl);  in udc_remote_wakeup()
1458 	writel(tmp, &dev->regs->ctl);  in udc_remote_wakeup()
1527 	tmp = readl(&dev->regs->ctl);  in udc_basic_init()
1530 	writel(tmp, &dev->regs->ctl);  in udc_basic_init()
1625 			ep->dma = &dev->regs->ctl;  in udc_setup_endpoints()
1631 				reg = readl(&dev->ep[tmp].regs->ctl);  in udc_setup_endpoints()
1633 				writel(reg, &dev->ep[tmp].regs->ctl);  in udc_setup_endpoints()
1782 			tmp = readl(&udc->regs->ctl);  in udc_timer_function()
1784 			writel(tmp, &udc->regs->ctl);  in udc_timer_function()
1824 		tmp = readl(&ep->regs->ctl);  in udc_handle_halt_state()
1841 			writel(tmp, &ep->regs->ctl);  in udc_handle_halt_state()
1890 	tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);  in activate_control_endpoints()
1892 	writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);  in activate_control_endpoints()
1955 		tmp = readl(&dev->regs->ctl);  in activate_control_endpoints()
1963 		writel(tmp, &dev->regs->ctl);  in activate_control_endpoints()
1967 	tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);  in activate_control_endpoints()
1969 	writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);  in activate_control_endpoints()
1974 	tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);  in activate_control_endpoints()
1976 	writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);  in activate_control_endpoints()
2013 	tmp = readl(&dev->regs->ctl);  in amd5536_udc_start()
2015 	writel(tmp, &dev->regs->ctl);  in amd5536_udc_start()
2054 	tmp = readl(&dev->regs->ctl);  in amd5536_udc_stop()
2056 	writel(tmp, &dev->regs->ctl);  in amd5536_udc_stop()
2073 			reg = readl(&dev->ep[tmp].regs->ctl);  in udc_process_cnak_queue()
2075 			writel(reg, &dev->ep[tmp].regs->ctl);  in udc_process_cnak_queue()
2084 		reg = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);  in udc_process_cnak_queue()
2086 		writel(reg, &dev->ep[UDC_EP0OUT_IX].regs->ctl);  in udc_process_cnak_queue()
2470 					tmp = readl(&ep->regs->ctl);  in udc_data_in_isr()
2472 					writel(tmp, &ep->regs->ctl);  in udc_data_in_isr()
2534 		tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);  in udc_control_out_isr()
2536 		writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);  in udc_control_out_isr()
2616 		tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);  in udc_control_out_isr()
2622 			writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);  in udc_control_out_isr()
2629 			writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);  in udc_control_out_isr()
2636 			tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);  in udc_control_out_isr()
2638 			writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);  in udc_control_out_isr()
2745 			tmp = readl(&ep->regs->ctl);  in udc_control_in_isr()
2747 			writel(tmp, &ep->regs->ctl);  in udc_control_in_isr()
2766 					readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);  in udc_control_in_isr()
2769 					&dev->ep[UDC_EP0IN_IX].regs->ctl);  in udc_control_in_isr()
2861 			tmp = readl(&ep->regs->ctl);  in udc_dev_isr()
2863 			writel(tmp, &ep->regs->ctl);  in udc_dev_isr()
2920 			tmp = readl(&ep->regs->ctl);  in udc_dev_isr()
2922 			writel(tmp, &ep->regs->ctl);  in udc_dev_isr()
3179 	dev->ep[UDC_EP0IN_IX].dma = &dev->regs->ctl;  in init_dma_pools()
3273 	reg = readl(&dev->regs->ctl);  in udc_probe()
3275 	writel(reg, &dev->regs->ctl);  in udc_probe()