974 				|| ep->num == UDC_EP0IN_IX) {  in prep_dma()
1168 				tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);  in udc_queue()
1170 				writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);  in udc_queue()
1171 				dev->ep[UDC_EP0IN_IX].naking = 0;  in udc_queue()
1172 				UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX],  in udc_queue()
1173 							UDC_EP0IN_IX);  in udc_queue()
1628 			if (tmp != UDC_EP0IN_IX && tmp != UDC_EP0OUT_IX  in udc_setup_endpoints()
1641 		usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0IN_IX].ep,  in udc_setup_endpoints()
1646 		usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0IN_IX].ep,  in udc_setup_endpoints()
1656 	dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IX].ep;  in udc_setup_endpoints()
1657 	dev->ep[UDC_EP0IN_IX].halted = 0;  in udc_setup_endpoints()
1725 			&dev->ep[UDC_EP0IN_IX]);  in udc_tasklet_disconnect()
1890 	tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);  in activate_control_endpoints()
1892 	writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);  in activate_control_endpoints()
1895 	dev->ep[UDC_EP0IN_IX].in = 1;  in activate_control_endpoints()
1899 	tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufin_framenum);  in activate_control_endpoints()
1906 	writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufin_framenum);  in activate_control_endpoints()
1909 	tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt);  in activate_control_endpoints()
1916 	writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt);  in activate_control_endpoints()
1967 	tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);  in activate_control_endpoints()
1969 	writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);  in activate_control_endpoints()
1970 	dev->ep[UDC_EP0IN_IX].naking = 0;  in activate_control_endpoints()
1971 	UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX], UDC_EP0IN_IX);  in activate_control_endpoints()
2007 		dev->ep[UDC_EP0IN_IX].ep.driver_data;  in amd5536_udc_start()
2534 		tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);  in udc_control_out_isr()
2536 		writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);  in udc_control_out_isr()
2537 		dev->ep[UDC_EP0IN_IX].naking = 1;  in udc_control_out_isr()
2559 			dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IX].ep;  in udc_control_out_isr()
2616 		tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);  in udc_control_out_isr()
2622 			writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);  in udc_control_out_isr()
2623 			dev->ep[UDC_EP0IN_IX].naking = 0;  in udc_control_out_isr()
2624 			UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX], UDC_EP0IN_IX);  in udc_control_out_isr()
2629 			writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);  in udc_control_out_isr()
2718 	ep = &dev->ep[UDC_EP0IN_IX];  in udc_control_in_isr()
2723 	tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->sts);  in udc_control_in_isr()
2731 				&dev->ep[UDC_EP0IN_IX].regs->sts);  in udc_control_in_isr()
2740 				&dev->ep[UDC_EP0IN_IX].regs->sts);  in udc_control_in_isr()
2766 					readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);  in udc_control_in_isr()
2769 					&dev->ep[UDC_EP0IN_IX].regs->ctl);  in udc_control_in_isr()
2801 				&dev->ep[UDC_EP0IN_IX].regs->sts);  in udc_control_in_isr()
2954 		empty_req_queue(&dev->ep[UDC_EP0IN_IX]);  in udc_dev_isr()
2955 		ep_init(dev->regs, &dev->ep[UDC_EP0IN_IX]);  in udc_dev_isr()
3003 		empty_req_queue(&dev->ep[UDC_EP0IN_IX]);  in udc_dev_isr()
3004 		ep_init(dev->regs, &dev->ep[UDC_EP0IN_IX]);  in udc_dev_isr()
3179 	dev->ep[UDC_EP0IN_IX].dma = &dev->regs->ctl;  in init_dma_pools()