Lines Matching refs:hsotg
67 static int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) in dwc2_backup_host_registers() argument
72 dev_dbg(hsotg->dev, "%s\n", __func__); in dwc2_backup_host_registers()
75 hr = &hsotg->hr_backup; in dwc2_backup_host_registers()
76 hr->hcfg = dwc2_readl(hsotg->regs + HCFG); in dwc2_backup_host_registers()
77 hr->haintmsk = dwc2_readl(hsotg->regs + HAINTMSK); in dwc2_backup_host_registers()
78 for (i = 0; i < hsotg->core_params->host_channels; ++i) in dwc2_backup_host_registers()
79 hr->hcintmsk[i] = dwc2_readl(hsotg->regs + HCINTMSK(i)); in dwc2_backup_host_registers()
81 hr->hprt0 = dwc2_read_hprt0(hsotg); in dwc2_backup_host_registers()
82 hr->hfir = dwc2_readl(hsotg->regs + HFIR); in dwc2_backup_host_registers()
95 static int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) in dwc2_restore_host_registers() argument
100 dev_dbg(hsotg->dev, "%s\n", __func__); in dwc2_restore_host_registers()
103 hr = &hsotg->hr_backup; in dwc2_restore_host_registers()
105 dev_err(hsotg->dev, "%s: no host registers to restore\n", in dwc2_restore_host_registers()
111 dwc2_writel(hr->hcfg, hsotg->regs + HCFG); in dwc2_restore_host_registers()
112 dwc2_writel(hr->haintmsk, hsotg->regs + HAINTMSK); in dwc2_restore_host_registers()
114 for (i = 0; i < hsotg->core_params->host_channels; ++i) in dwc2_restore_host_registers()
115 dwc2_writel(hr->hcintmsk[i], hsotg->regs + HCINTMSK(i)); in dwc2_restore_host_registers()
117 dwc2_writel(hr->hprt0, hsotg->regs + HPRT0); in dwc2_restore_host_registers()
118 dwc2_writel(hr->hfir, hsotg->regs + HFIR); in dwc2_restore_host_registers()
119 hsotg->frame_number = 0; in dwc2_restore_host_registers()
124 static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) in dwc2_backup_host_registers() argument
127 static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) in dwc2_restore_host_registers() argument
140 static int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) in dwc2_backup_device_registers() argument
145 dev_dbg(hsotg->dev, "%s\n", __func__); in dwc2_backup_device_registers()
148 dr = &hsotg->dr_backup; in dwc2_backup_device_registers()
150 dr->dcfg = dwc2_readl(hsotg->regs + DCFG); in dwc2_backup_device_registers()
151 dr->dctl = dwc2_readl(hsotg->regs + DCTL); in dwc2_backup_device_registers()
152 dr->daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); in dwc2_backup_device_registers()
153 dr->diepmsk = dwc2_readl(hsotg->regs + DIEPMSK); in dwc2_backup_device_registers()
154 dr->doepmsk = dwc2_readl(hsotg->regs + DOEPMSK); in dwc2_backup_device_registers()
156 for (i = 0; i < hsotg->num_of_eps; i++) { in dwc2_backup_device_registers()
158 dr->diepctl[i] = dwc2_readl(hsotg->regs + DIEPCTL(i)); in dwc2_backup_device_registers()
166 dr->dieptsiz[i] = dwc2_readl(hsotg->regs + DIEPTSIZ(i)); in dwc2_backup_device_registers()
167 dr->diepdma[i] = dwc2_readl(hsotg->regs + DIEPDMA(i)); in dwc2_backup_device_registers()
170 dr->doepctl[i] = dwc2_readl(hsotg->regs + DOEPCTL(i)); in dwc2_backup_device_registers()
178 dr->doeptsiz[i] = dwc2_readl(hsotg->regs + DOEPTSIZ(i)); in dwc2_backup_device_registers()
179 dr->doepdma[i] = dwc2_readl(hsotg->regs + DOEPDMA(i)); in dwc2_backup_device_registers()
192 static int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg) in dwc2_restore_device_registers() argument
198 dev_dbg(hsotg->dev, "%s\n", __func__); in dwc2_restore_device_registers()
201 dr = &hsotg->dr_backup; in dwc2_restore_device_registers()
203 dev_err(hsotg->dev, "%s: no device registers to restore\n", in dwc2_restore_device_registers()
209 dwc2_writel(dr->dcfg, hsotg->regs + DCFG); in dwc2_restore_device_registers()
210 dwc2_writel(dr->dctl, hsotg->regs + DCTL); in dwc2_restore_device_registers()
211 dwc2_writel(dr->daintmsk, hsotg->regs + DAINTMSK); in dwc2_restore_device_registers()
212 dwc2_writel(dr->diepmsk, hsotg->regs + DIEPMSK); in dwc2_restore_device_registers()
213 dwc2_writel(dr->doepmsk, hsotg->regs + DOEPMSK); in dwc2_restore_device_registers()
215 for (i = 0; i < hsotg->num_of_eps; i++) { in dwc2_restore_device_registers()
217 dwc2_writel(dr->diepctl[i], hsotg->regs + DIEPCTL(i)); in dwc2_restore_device_registers()
218 dwc2_writel(dr->dieptsiz[i], hsotg->regs + DIEPTSIZ(i)); in dwc2_restore_device_registers()
219 dwc2_writel(dr->diepdma[i], hsotg->regs + DIEPDMA(i)); in dwc2_restore_device_registers()
222 dwc2_writel(dr->doepctl[i], hsotg->regs + DOEPCTL(i)); in dwc2_restore_device_registers()
223 dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i)); in dwc2_restore_device_registers()
224 dwc2_writel(dr->doepdma[i], hsotg->regs + DOEPDMA(i)); in dwc2_restore_device_registers()
228 dctl = dwc2_readl(hsotg->regs + DCTL); in dwc2_restore_device_registers()
230 dwc2_writel(dctl, hsotg->regs + DCTL); in dwc2_restore_device_registers()
235 static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) in dwc2_backup_device_registers() argument
238 static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg) in dwc2_restore_device_registers() argument
249 static int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg) in dwc2_backup_global_registers() argument
255 gr = &hsotg->gr_backup; in dwc2_backup_global_registers()
257 gr->gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); in dwc2_backup_global_registers()
258 gr->gintmsk = dwc2_readl(hsotg->regs + GINTMSK); in dwc2_backup_global_registers()
259 gr->gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); in dwc2_backup_global_registers()
260 gr->gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); in dwc2_backup_global_registers()
261 gr->grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); in dwc2_backup_global_registers()
262 gr->gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); in dwc2_backup_global_registers()
263 gr->hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ); in dwc2_backup_global_registers()
264 gr->gdfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG); in dwc2_backup_global_registers()
266 gr->dtxfsiz[i] = dwc2_readl(hsotg->regs + DPTXFSIZN(i)); in dwc2_backup_global_registers()
279 static int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg) in dwc2_restore_global_registers() argument
284 dev_dbg(hsotg->dev, "%s\n", __func__); in dwc2_restore_global_registers()
287 gr = &hsotg->gr_backup; in dwc2_restore_global_registers()
289 dev_err(hsotg->dev, "%s: no global registers to restore\n", in dwc2_restore_global_registers()
295 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); in dwc2_restore_global_registers()
296 dwc2_writel(gr->gotgctl, hsotg->regs + GOTGCTL); in dwc2_restore_global_registers()
297 dwc2_writel(gr->gintmsk, hsotg->regs + GINTMSK); in dwc2_restore_global_registers()
298 dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG); in dwc2_restore_global_registers()
299 dwc2_writel(gr->gahbcfg, hsotg->regs + GAHBCFG); in dwc2_restore_global_registers()
300 dwc2_writel(gr->grxfsiz, hsotg->regs + GRXFSIZ); in dwc2_restore_global_registers()
301 dwc2_writel(gr->gnptxfsiz, hsotg->regs + GNPTXFSIZ); in dwc2_restore_global_registers()
302 dwc2_writel(gr->hptxfsiz, hsotg->regs + HPTXFSIZ); in dwc2_restore_global_registers()
303 dwc2_writel(gr->gdfifocfg, hsotg->regs + GDFIFOCFG); in dwc2_restore_global_registers()
305 dwc2_writel(gr->dtxfsiz[i], hsotg->regs + DPTXFSIZN(i)); in dwc2_restore_global_registers()
316 int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore) in dwc2_exit_hibernation() argument
321 if (!hsotg->core_params->hibernation) in dwc2_exit_hibernation()
324 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); in dwc2_exit_hibernation()
326 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); in dwc2_exit_hibernation()
328 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); in dwc2_exit_hibernation()
330 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); in dwc2_exit_hibernation()
332 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); in dwc2_exit_hibernation()
334 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); in dwc2_exit_hibernation()
338 ret = dwc2_restore_global_registers(hsotg); in dwc2_exit_hibernation()
340 dev_err(hsotg->dev, "%s: failed to restore registers\n", in dwc2_exit_hibernation()
344 if (dwc2_is_host_mode(hsotg)) { in dwc2_exit_hibernation()
345 ret = dwc2_restore_host_registers(hsotg); in dwc2_exit_hibernation()
347 dev_err(hsotg->dev, "%s: failed to restore host registers\n", in dwc2_exit_hibernation()
352 ret = dwc2_restore_device_registers(hsotg); in dwc2_exit_hibernation()
354 dev_err(hsotg->dev, "%s: failed to restore device registers\n", in dwc2_exit_hibernation()
369 int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg) in dwc2_enter_hibernation() argument
374 if (!hsotg->core_params->hibernation) in dwc2_enter_hibernation()
378 ret = dwc2_backup_global_registers(hsotg); in dwc2_enter_hibernation()
380 dev_err(hsotg->dev, "%s: failed to backup global registers\n", in dwc2_enter_hibernation()
385 if (dwc2_is_host_mode(hsotg)) { in dwc2_enter_hibernation()
386 ret = dwc2_backup_host_registers(hsotg); in dwc2_enter_hibernation()
388 dev_err(hsotg->dev, "%s: failed to backup host registers\n", in dwc2_enter_hibernation()
393 ret = dwc2_backup_device_registers(hsotg); in dwc2_enter_hibernation()
395 dev_err(hsotg->dev, "%s: failed to backup device registers\n", in dwc2_enter_hibernation()
405 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); in dwc2_enter_hibernation()
408 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); in dwc2_enter_hibernation()
411 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); in dwc2_enter_hibernation()
415 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); in dwc2_enter_hibernation()
419 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); in dwc2_enter_hibernation()
430 static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg) in dwc2_enable_common_interrupts() argument
435 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT); in dwc2_enable_common_interrupts()
438 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); in dwc2_enable_common_interrupts()
443 if (hsotg->core_params->dma_enable <= 0) in dwc2_enable_common_interrupts()
445 if (hsotg->core_params->external_id_pin_ctl <= 0) in dwc2_enable_common_interrupts()
451 dwc2_writel(intmsk, hsotg->regs + GINTMSK); in dwc2_enable_common_interrupts()
458 static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg) in dwc2_init_fs_ls_pclk_sel() argument
462 if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && in dwc2_init_fs_ls_pclk_sel()
463 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && in dwc2_init_fs_ls_pclk_sel()
464 hsotg->core_params->ulpi_fs_ls > 0) || in dwc2_init_fs_ls_pclk_sel()
465 hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) { in dwc2_init_fs_ls_pclk_sel()
473 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val); in dwc2_init_fs_ls_pclk_sel()
474 hcfg = dwc2_readl(hsotg->regs + HCFG); in dwc2_init_fs_ls_pclk_sel()
477 dwc2_writel(hcfg, hsotg->regs + HCFG); in dwc2_init_fs_ls_pclk_sel()
484 static int dwc2_core_reset(struct dwc2_hsotg *hsotg) in dwc2_core_reset() argument
490 dev_vdbg(hsotg->dev, "%s()\n", __func__); in dwc2_core_reset()
495 greset = dwc2_readl(hsotg->regs + GRSTCTL); in dwc2_core_reset()
497 dev_warn(hsotg->dev, in dwc2_core_reset()
507 dwc2_writel(greset, hsotg->regs + GRSTCTL); in dwc2_core_reset()
510 greset = dwc2_readl(hsotg->regs + GRSTCTL); in dwc2_core_reset()
512 dev_warn(hsotg->dev, in dwc2_core_reset()
519 if (hsotg->dr_mode == USB_DR_MODE_HOST) { in dwc2_core_reset()
520 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); in dwc2_core_reset()
523 dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG); in dwc2_core_reset()
524 } else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) { in dwc2_core_reset()
525 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); in dwc2_core_reset()
528 dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG); in dwc2_core_reset()
529 } else if (hsotg->dr_mode == USB_DR_MODE_OTG) { in dwc2_core_reset()
530 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); in dwc2_core_reset()
533 dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG); in dwc2_core_reset()
545 static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) in dwc2_fs_phy_init() argument
555 dev_dbg(hsotg->dev, "FS PHY selected\n"); in dwc2_fs_phy_init()
556 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); in dwc2_fs_phy_init()
558 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); in dwc2_fs_phy_init()
561 retval = dwc2_core_reset(hsotg); in dwc2_fs_phy_init()
563 dev_err(hsotg->dev, "%s() Reset failed, aborting", in dwc2_fs_phy_init()
574 if (dwc2_is_host_mode(hsotg)) in dwc2_fs_phy_init()
575 dwc2_init_fs_ls_pclk_sel(hsotg); in dwc2_fs_phy_init()
577 if (hsotg->core_params->i2c_enable > 0) { in dwc2_fs_phy_init()
578 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n"); in dwc2_fs_phy_init()
581 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); in dwc2_fs_phy_init()
583 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); in dwc2_fs_phy_init()
586 i2cctl = dwc2_readl(hsotg->regs + GI2CCTL); in dwc2_fs_phy_init()
590 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL); in dwc2_fs_phy_init()
592 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL); in dwc2_fs_phy_init()
598 static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) in dwc2_hs_phy_init() argument
606 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); in dwc2_hs_phy_init()
613 switch (hsotg->core_params->phy_type) { in dwc2_hs_phy_init()
616 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n"); in dwc2_hs_phy_init()
619 if (hsotg->core_params->phy_ulpi_ddr > 0) in dwc2_hs_phy_init()
624 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n"); in dwc2_hs_phy_init()
626 if (hsotg->core_params->phy_utmi_width == 16) in dwc2_hs_phy_init()
630 dev_err(hsotg->dev, "FS PHY selected at HS!\n"); in dwc2_hs_phy_init()
634 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); in dwc2_hs_phy_init()
637 retval = dwc2_core_reset(hsotg); in dwc2_hs_phy_init()
639 dev_err(hsotg->dev, "%s() Reset failed, aborting", in dwc2_hs_phy_init()
647 static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) in dwc2_phy_init() argument
652 if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL && in dwc2_phy_init()
653 hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) { in dwc2_phy_init()
655 retval = dwc2_fs_phy_init(hsotg, select_phy); in dwc2_phy_init()
660 retval = dwc2_hs_phy_init(hsotg, select_phy); in dwc2_phy_init()
665 if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && in dwc2_phy_init()
666 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && in dwc2_phy_init()
667 hsotg->core_params->ulpi_fs_ls > 0) { in dwc2_phy_init()
668 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n"); in dwc2_phy_init()
669 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); in dwc2_phy_init()
672 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); in dwc2_phy_init()
674 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); in dwc2_phy_init()
677 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); in dwc2_phy_init()
683 static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg) in dwc2_gahbcfg_init() argument
685 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); in dwc2_gahbcfg_init()
687 switch (hsotg->hw_params.arch) { in dwc2_gahbcfg_init()
689 dev_err(hsotg->dev, "External DMA Mode not supported\n"); in dwc2_gahbcfg_init()
693 dev_dbg(hsotg->dev, "Internal DMA Mode\n"); in dwc2_gahbcfg_init()
694 if (hsotg->core_params->ahbcfg != -1) { in dwc2_gahbcfg_init()
696 ahbcfg |= hsotg->core_params->ahbcfg & in dwc2_gahbcfg_init()
703 dev_dbg(hsotg->dev, "Slave Only Mode\n"); in dwc2_gahbcfg_init()
707 dev_dbg(hsotg->dev, "dma_enable:%d dma_desc_enable:%d\n", in dwc2_gahbcfg_init()
708 hsotg->core_params->dma_enable, in dwc2_gahbcfg_init()
709 hsotg->core_params->dma_desc_enable); in dwc2_gahbcfg_init()
711 if (hsotg->core_params->dma_enable > 0) { in dwc2_gahbcfg_init()
712 if (hsotg->core_params->dma_desc_enable > 0) in dwc2_gahbcfg_init()
713 dev_dbg(hsotg->dev, "Using Descriptor DMA mode\n"); in dwc2_gahbcfg_init()
715 dev_dbg(hsotg->dev, "Using Buffer DMA mode\n"); in dwc2_gahbcfg_init()
717 dev_dbg(hsotg->dev, "Using Slave mode\n"); in dwc2_gahbcfg_init()
718 hsotg->core_params->dma_desc_enable = 0; in dwc2_gahbcfg_init()
721 if (hsotg->core_params->dma_enable > 0) in dwc2_gahbcfg_init()
724 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); in dwc2_gahbcfg_init()
729 static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg) in dwc2_gusbcfg_init() argument
733 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); in dwc2_gusbcfg_init()
736 switch (hsotg->hw_params.op_mode) { in dwc2_gusbcfg_init()
738 if (hsotg->core_params->otg_cap == in dwc2_gusbcfg_init()
741 if (hsotg->core_params->otg_cap != in dwc2_gusbcfg_init()
749 if (hsotg->core_params->otg_cap != in dwc2_gusbcfg_init()
761 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); in dwc2_gusbcfg_init()
772 int dwc2_core_init(struct dwc2_hsotg *hsotg, bool select_phy, int irq) in dwc2_core_init() argument
777 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); in dwc2_core_init()
779 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); in dwc2_core_init()
783 if (hsotg->core_params->phy_ulpi_ext_vbus == in dwc2_core_init()
789 if (hsotg->core_params->ts_dline > 0) in dwc2_core_init()
792 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); in dwc2_core_init()
795 retval = dwc2_core_reset(hsotg); in dwc2_core_init()
797 dev_err(hsotg->dev, "%s(): Reset failed, aborting\n", in dwc2_core_init()
805 retval = dwc2_phy_init(hsotg, select_phy); in dwc2_core_init()
810 retval = dwc2_gahbcfg_init(hsotg); in dwc2_core_init()
815 dwc2_gusbcfg_init(hsotg); in dwc2_core_init()
818 otgctl = dwc2_readl(hsotg->regs + GOTGCTL); in dwc2_core_init()
820 if (hsotg->core_params->otg_ver > 0) in dwc2_core_init()
822 dwc2_writel(otgctl, hsotg->regs + GOTGCTL); in dwc2_core_init()
823 dev_dbg(hsotg->dev, "OTG VER PARAM: %d\n", hsotg->core_params->otg_ver); in dwc2_core_init()
826 hsotg->srp_success = 0; in dwc2_core_init()
829 dwc2_enable_common_interrupts(hsotg); in dwc2_core_init()
835 if (dwc2_is_host_mode(hsotg)) { in dwc2_core_init()
836 dev_dbg(hsotg->dev, "Host Mode\n"); in dwc2_core_init()
837 hsotg->op_state = OTG_STATE_A_HOST; in dwc2_core_init()
839 dev_dbg(hsotg->dev, "Device Mode\n"); in dwc2_core_init()
840 hsotg->op_state = OTG_STATE_B_PERIPHERAL; in dwc2_core_init()
851 void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg) in dwc2_enable_host_interrupts() argument
855 dev_dbg(hsotg->dev, "%s()\n", __func__); in dwc2_enable_host_interrupts()
858 dwc2_writel(0, hsotg->regs + GINTMSK); in dwc2_enable_host_interrupts()
859 dwc2_writel(0, hsotg->regs + HAINTMSK); in dwc2_enable_host_interrupts()
862 dwc2_enable_common_interrupts(hsotg); in dwc2_enable_host_interrupts()
865 intmsk = dwc2_readl(hsotg->regs + GINTMSK); in dwc2_enable_host_interrupts()
867 dwc2_writel(intmsk, hsotg->regs + GINTMSK); in dwc2_enable_host_interrupts()
875 void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg) in dwc2_disable_host_interrupts() argument
877 u32 intmsk = dwc2_readl(hsotg->regs + GINTMSK); in dwc2_disable_host_interrupts()
882 dwc2_writel(intmsk, hsotg->regs + GINTMSK); in dwc2_disable_host_interrupts()
892 static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg) in dwc2_calculate_dynamic_fifo() argument
894 struct dwc2_core_params *params = hsotg->core_params; in dwc2_calculate_dynamic_fifo()
895 struct dwc2_hw_params *hw = &hsotg->hw_params; in dwc2_calculate_dynamic_fifo()
948 dev_err(hsotg->dev, "invalid fifo sizes\n"); in dwc2_calculate_dynamic_fifo()
951 static void dwc2_config_fifos(struct dwc2_hsotg *hsotg) in dwc2_config_fifos() argument
953 struct dwc2_core_params *params = hsotg->core_params; in dwc2_config_fifos()
959 dwc2_calculate_dynamic_fifo(hsotg); in dwc2_config_fifos()
962 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); in dwc2_config_fifos()
963 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz); in dwc2_config_fifos()
967 dwc2_writel(grxfsiz, hsotg->regs + GRXFSIZ); in dwc2_config_fifos()
968 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n", in dwc2_config_fifos()
969 dwc2_readl(hsotg->regs + GRXFSIZ)); in dwc2_config_fifos()
972 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n", in dwc2_config_fifos()
973 dwc2_readl(hsotg->regs + GNPTXFSIZ)); in dwc2_config_fifos()
978 dwc2_writel(nptxfsiz, hsotg->regs + GNPTXFSIZ); in dwc2_config_fifos()
979 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n", in dwc2_config_fifos()
980 dwc2_readl(hsotg->regs + GNPTXFSIZ)); in dwc2_config_fifos()
983 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n", in dwc2_config_fifos()
984 dwc2_readl(hsotg->regs + HPTXFSIZ)); in dwc2_config_fifos()
990 dwc2_writel(hptxfsiz, hsotg->regs + HPTXFSIZ); in dwc2_config_fifos()
991 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n", in dwc2_config_fifos()
992 dwc2_readl(hsotg->regs + HPTXFSIZ)); in dwc2_config_fifos()
994 if (hsotg->core_params->en_multiple_tx_fifo > 0 && in dwc2_config_fifos()
995 hsotg->hw_params.snpsid <= DWC2_CORE_REV_2_94a) { in dwc2_config_fifos()
1000 dfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG); in dwc2_config_fifos()
1007 dwc2_writel(dfifocfg, hsotg->regs + GDFIFOCFG); in dwc2_config_fifos()
1021 void dwc2_core_host_init(struct dwc2_hsotg *hsotg) in dwc2_core_host_init() argument
1025 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); in dwc2_core_host_init()
1028 dwc2_writel(0, hsotg->regs + PCGCTL); in dwc2_core_host_init()
1031 dwc2_init_fs_ls_pclk_sel(hsotg); in dwc2_core_host_init()
1032 if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL) { in dwc2_core_host_init()
1033 hcfg = dwc2_readl(hsotg->regs + HCFG); in dwc2_core_host_init()
1035 dwc2_writel(hcfg, hsotg->regs + HCFG); in dwc2_core_host_init()
1043 if (hsotg->core_params->reload_ctl > 0) { in dwc2_core_host_init()
1044 hfir = dwc2_readl(hsotg->regs + HFIR); in dwc2_core_host_init()
1046 dwc2_writel(hfir, hsotg->regs + HFIR); in dwc2_core_host_init()
1049 if (hsotg->core_params->dma_desc_enable > 0) { in dwc2_core_host_init()
1050 u32 op_mode = hsotg->hw_params.op_mode; in dwc2_core_host_init()
1051 if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a || in dwc2_core_host_init()
1052 !hsotg->hw_params.dma_desc_enable || in dwc2_core_host_init()
1056 dev_err(hsotg->dev, in dwc2_core_host_init()
1058 dev_err(hsotg->dev, in dwc2_core_host_init()
1060 hsotg->core_params->dma_desc_enable = 0; in dwc2_core_host_init()
1062 hcfg = dwc2_readl(hsotg->regs + HCFG); in dwc2_core_host_init()
1064 dwc2_writel(hcfg, hsotg->regs + HCFG); in dwc2_core_host_init()
1069 dwc2_config_fifos(hsotg); in dwc2_core_host_init()
1073 otgctl = dwc2_readl(hsotg->regs + GOTGCTL); in dwc2_core_host_init()
1075 dwc2_writel(otgctl, hsotg->regs + GOTGCTL); in dwc2_core_host_init()
1078 dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */); in dwc2_core_host_init()
1079 dwc2_flush_rx_fifo(hsotg); in dwc2_core_host_init()
1082 otgctl = dwc2_readl(hsotg->regs + GOTGCTL); in dwc2_core_host_init()
1084 dwc2_writel(otgctl, hsotg->regs + GOTGCTL); in dwc2_core_host_init()
1086 if (hsotg->core_params->dma_desc_enable <= 0) { in dwc2_core_host_init()
1091 num_channels = hsotg->core_params->host_channels; in dwc2_core_host_init()
1093 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); in dwc2_core_host_init()
1097 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); in dwc2_core_host_init()
1104 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); in dwc2_core_host_init()
1107 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); in dwc2_core_host_init()
1108 dev_dbg(hsotg->dev, "%s: Halt channel %d\n", in dwc2_core_host_init()
1111 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); in dwc2_core_host_init()
1113 dev_err(hsotg->dev, in dwc2_core_host_init()
1124 dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state); in dwc2_core_host_init()
1125 if (hsotg->op_state == OTG_STATE_A_HOST) { in dwc2_core_host_init()
1126 u32 hprt0 = dwc2_read_hprt0(hsotg); in dwc2_core_host_init()
1128 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n", in dwc2_core_host_init()
1132 dwc2_writel(hprt0, hsotg->regs + HPRT0); in dwc2_core_host_init()
1136 dwc2_enable_host_interrupts(hsotg); in dwc2_core_host_init()
1139 static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg, in dwc2_hc_enable_slave_ints() argument
1147 dev_vdbg(hsotg->dev, "control/bulk\n"); in dwc2_hc_enable_slave_ints()
1175 dev_vdbg(hsotg->dev, "intr\n"); in dwc2_hc_enable_slave_ints()
1197 dev_vdbg(hsotg->dev, "isoc\n"); in dwc2_hc_enable_slave_ints()
1208 dev_err(hsotg->dev, "## Unknown EP type ##\n"); in dwc2_hc_enable_slave_ints()
1212 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); in dwc2_hc_enable_slave_ints()
1214 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); in dwc2_hc_enable_slave_ints()
1217 static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg, in dwc2_hc_enable_dma_ints() argument
1226 if (hsotg->core_params->dma_desc_enable <= 0) { in dwc2_hc_enable_dma_ints()
1228 dev_vdbg(hsotg->dev, "desc DMA disabled\n"); in dwc2_hc_enable_dma_ints()
1232 dev_vdbg(hsotg->dev, "desc DMA enabled\n"); in dwc2_hc_enable_dma_ints()
1240 dev_vdbg(hsotg->dev, "setting ACK\n"); in dwc2_hc_enable_dma_ints()
1249 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); in dwc2_hc_enable_dma_ints()
1251 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); in dwc2_hc_enable_dma_ints()
1254 static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg, in dwc2_hc_enable_ints() argument
1259 if (hsotg->core_params->dma_enable > 0) { in dwc2_hc_enable_ints()
1261 dev_vdbg(hsotg->dev, "DMA enabled\n"); in dwc2_hc_enable_ints()
1262 dwc2_hc_enable_dma_ints(hsotg, chan); in dwc2_hc_enable_ints()
1265 dev_vdbg(hsotg->dev, "DMA disabled\n"); in dwc2_hc_enable_ints()
1266 dwc2_hc_enable_slave_ints(hsotg, chan); in dwc2_hc_enable_ints()
1270 intmsk = dwc2_readl(hsotg->regs + HAINTMSK); in dwc2_hc_enable_ints()
1272 dwc2_writel(intmsk, hsotg->regs + HAINTMSK); in dwc2_hc_enable_ints()
1274 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk); in dwc2_hc_enable_ints()
1277 intmsk = dwc2_readl(hsotg->regs + GINTMSK); in dwc2_hc_enable_ints()
1279 dwc2_writel(intmsk, hsotg->regs + GINTMSK); in dwc2_hc_enable_ints()
1281 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk); in dwc2_hc_enable_ints()
1295 void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) in dwc2_hc_init() argument
1303 dev_vdbg(hsotg->dev, "%s()\n", __func__); in dwc2_hc_init()
1308 dwc2_writel(hcintmsk, hsotg->regs + HCINT(hc_num)); in dwc2_hc_init()
1311 dwc2_hc_enable_ints(hsotg, chan); in dwc2_hc_init()
1325 dwc2_writel(hcchar, hsotg->regs + HCCHAR(hc_num)); in dwc2_hc_init()
1327 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n", in dwc2_hc_init()
1330 dev_vdbg(hsotg->dev, "%s: Channel %d\n", in dwc2_hc_init()
1332 dev_vdbg(hsotg->dev, " Dev Addr: %d\n", in dwc2_hc_init()
1334 dev_vdbg(hsotg->dev, " Ep Num: %d\n", in dwc2_hc_init()
1336 dev_vdbg(hsotg->dev, " Is In: %d\n", in dwc2_hc_init()
1338 dev_vdbg(hsotg->dev, " Is Low Speed: %d\n", in dwc2_hc_init()
1340 dev_vdbg(hsotg->dev, " Ep Type: %d\n", in dwc2_hc_init()
1342 dev_vdbg(hsotg->dev, " Max Pkt: %d\n", in dwc2_hc_init()
1349 dev_vdbg(hsotg->dev, in dwc2_hc_init()
1362 dev_vdbg(hsotg->dev, " comp split %d\n", in dwc2_hc_init()
1364 dev_vdbg(hsotg->dev, " xact pos %d\n", in dwc2_hc_init()
1366 dev_vdbg(hsotg->dev, " hub addr %d\n", in dwc2_hc_init()
1368 dev_vdbg(hsotg->dev, " hub port %d\n", in dwc2_hc_init()
1370 dev_vdbg(hsotg->dev, " is_in %d\n", in dwc2_hc_init()
1372 dev_vdbg(hsotg->dev, " Max Pkt %d\n", in dwc2_hc_init()
1374 dev_vdbg(hsotg->dev, " xferlen %d\n", in dwc2_hc_init()
1379 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(hc_num)); in dwc2_hc_init()
1410 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, in dwc2_hc_halt() argument
1416 dev_vdbg(hsotg->dev, "%s()\n", __func__); in dwc2_hc_halt()
1418 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status); in dwc2_hc_halt()
1430 dev_vdbg(hsotg->dev, "dequeue/error\n"); in dwc2_hc_halt()
1431 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); in dwc2_hc_halt()
1438 dwc2_writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num)); in dwc2_hc_halt()
1447 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); in dwc2_hc_halt()
1469 dev_vdbg(hsotg->dev, in dwc2_hc_halt()
1475 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); in dwc2_hc_halt()
1479 if (hsotg->core_params->dma_desc_enable <= 0) { in dwc2_hc_halt()
1481 dev_vdbg(hsotg->dev, "desc DMA disabled\n"); in dwc2_hc_halt()
1485 dev_dbg(hsotg->dev, "desc DMA enabled\n"); in dwc2_hc_halt()
1489 if (hsotg->core_params->dma_enable <= 0) { in dwc2_hc_halt()
1491 dev_vdbg(hsotg->dev, "DMA not enabled\n"); in dwc2_hc_halt()
1497 dev_vdbg(hsotg->dev, "control/bulk\n"); in dwc2_hc_halt()
1498 nptxsts = dwc2_readl(hsotg->regs + GNPTXSTS); in dwc2_hc_halt()
1500 dev_vdbg(hsotg->dev, "Disabling channel\n"); in dwc2_hc_halt()
1505 dev_vdbg(hsotg->dev, "isoc/intr\n"); in dwc2_hc_halt()
1506 hptxsts = dwc2_readl(hsotg->regs + HPTXSTS); in dwc2_hc_halt()
1508 hsotg->queuing_high_bandwidth) { in dwc2_hc_halt()
1510 dev_vdbg(hsotg->dev, "Disabling channel\n"); in dwc2_hc_halt()
1516 dev_vdbg(hsotg->dev, "DMA enabled\n"); in dwc2_hc_halt()
1519 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); in dwc2_hc_halt()
1524 dev_vdbg(hsotg->dev, "Channel enabled\n"); in dwc2_hc_halt()
1529 dev_vdbg(hsotg->dev, "Channel disabled\n"); in dwc2_hc_halt()
1534 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, in dwc2_hc_halt()
1536 dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n", in dwc2_hc_halt()
1538 dev_vdbg(hsotg->dev, " halt_pending: %d\n", in dwc2_hc_halt()
1540 dev_vdbg(hsotg->dev, " halt_on_queue: %d\n", in dwc2_hc_halt()
1542 dev_vdbg(hsotg->dev, " halt_status: %d\n", in dwc2_hc_halt()
1556 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) in dwc2_hc_cleanup() argument
1566 dwc2_writel(0, hsotg->regs + HCINTMSK(chan->hc_num)); in dwc2_hc_cleanup()
1569 dwc2_writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num)); in dwc2_hc_cleanup()
1582 static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg, in dwc2_hc_set_even_odd_frame() argument
1588 if (!(dwc2_hcd_get_frame_number(hsotg) & 0x1)) in dwc2_hc_set_even_odd_frame()
1629 static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg, in dwc2_hc_write_packet() argument
1640 dev_vdbg(hsotg->dev, "%s()\n", __func__); in dwc2_hc_write_packet()
1642 data_fifo = (u32 __iomem *)(hsotg->regs + HCFIFO(chan->hc_num)); in dwc2_hc_write_packet()
1702 void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, in dwc2_hc_start_transfer() argument
1705 u32 max_hc_xfer_size = hsotg->core_params->max_transfer_size; in dwc2_hc_start_transfer()
1706 u16 max_hc_pkt_count = hsotg->core_params->max_packet_count; in dwc2_hc_start_transfer()
1712 dev_vdbg(hsotg->dev, "%s()\n", __func__); in dwc2_hc_start_transfer()
1715 if (hsotg->core_params->dma_enable <= 0) { in dwc2_hc_start_transfer()
1717 dev_vdbg(hsotg->dev, "ping, no DMA\n"); in dwc2_hc_start_transfer()
1718 dwc2_hc_do_ping(hsotg, chan); in dwc2_hc_start_transfer()
1723 dev_vdbg(hsotg->dev, "ping, DMA\n"); in dwc2_hc_start_transfer()
1730 dev_vdbg(hsotg->dev, "split\n"); in dwc2_hc_start_transfer()
1748 dev_vdbg(hsotg->dev, "no split\n"); in dwc2_hc_start_transfer()
1814 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); in dwc2_hc_start_transfer()
1816 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n", in dwc2_hc_start_transfer()
1819 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, in dwc2_hc_start_transfer()
1821 dev_vdbg(hsotg->dev, " Xfer Size: %d\n", in dwc2_hc_start_transfer()
1824 dev_vdbg(hsotg->dev, " Num Pkts: %d\n", in dwc2_hc_start_transfer()
1827 dev_vdbg(hsotg->dev, " Start PID: %d\n", in dwc2_hc_start_transfer()
1832 if (hsotg->core_params->dma_enable > 0) { in dwc2_hc_start_transfer()
1837 dev_vdbg(hsotg->dev, "align_buf\n"); in dwc2_hc_start_transfer()
1842 dwc2_writel((u32)dma_addr, hsotg->regs + HCDMA(chan->hc_num)); in dwc2_hc_start_transfer()
1844 dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n", in dwc2_hc_start_transfer()
1850 u32 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num)); in dwc2_hc_start_transfer()
1853 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num)); in dwc2_hc_start_transfer()
1856 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); in dwc2_hc_start_transfer()
1860 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); in dwc2_hc_start_transfer()
1863 dev_warn(hsotg->dev, in dwc2_hc_start_transfer()
1872 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n", in dwc2_hc_start_transfer()
1876 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); in dwc2_hc_start_transfer()
1878 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, in dwc2_hc_start_transfer()
1884 if (hsotg->core_params->dma_enable <= 0 && in dwc2_hc_start_transfer()
1887 dwc2_hc_write_packet(hsotg, chan); in dwc2_hc_start_transfer()
1904 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, in dwc2_hc_start_transfer_ddma() argument
1928 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, in dwc2_hc_start_transfer_ddma()
1930 dev_vdbg(hsotg->dev, " Start PID: %d\n", in dwc2_hc_start_transfer_ddma()
1932 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1); in dwc2_hc_start_transfer_ddma()
1935 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); in dwc2_hc_start_transfer_ddma()
1941 dwc2_writel(hc_dma, hsotg->regs + HCDMA(chan->hc_num)); in dwc2_hc_start_transfer_ddma()
1943 dev_vdbg(hsotg->dev, "Wrote %08x to HCDMA(%d)\n", in dwc2_hc_start_transfer_ddma()
1946 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); in dwc2_hc_start_transfer_ddma()
1952 dev_warn(hsotg->dev, in dwc2_hc_start_transfer_ddma()
1961 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n", in dwc2_hc_start_transfer_ddma()
1965 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); in dwc2_hc_start_transfer_ddma()
1967 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, in dwc2_hc_start_transfer_ddma()
1994 int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, in dwc2_hc_continue_transfer() argument
1998 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, in dwc2_hc_continue_transfer()
2022 u32 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); in dwc2_hc_continue_transfer()
2024 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); in dwc2_hc_continue_transfer()
2028 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n", in dwc2_hc_continue_transfer()
2030 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); in dwc2_hc_continue_transfer()
2040 u32 hcchar = dwc2_readl(hsotg->regs + in dwc2_hc_continue_transfer()
2043 dwc2_hc_set_even_odd_frame(hsotg, chan, in dwc2_hc_continue_transfer()
2048 dwc2_hc_write_packet(hsotg, chan); in dwc2_hc_continue_transfer()
2065 void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) in dwc2_hc_do_ping() argument
2071 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, in dwc2_hc_do_ping()
2077 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); in dwc2_hc_do_ping()
2079 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); in dwc2_hc_do_ping()
2082 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); in dwc2_hc_do_ping()
2095 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg) in dwc2_calc_frame_interval() argument
2101 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); in dwc2_calc_frame_interval()
2102 hprt0 = dwc2_readl(hsotg->regs + HPRT0); in dwc2_calc_frame_interval()
2107 if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type == in dwc2_calc_frame_interval()
2120 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI) in dwc2_calc_frame_interval()
2123 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) in dwc2_calc_frame_interval()
2142 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes) in dwc2_read_packet() argument
2144 u32 __iomem *fifo = hsotg->regs + HCFIFO(0); in dwc2_read_packet()
2155 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes); in dwc2_read_packet()
2169 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg) in dwc2_dump_host_registers() argument
2175 dev_dbg(hsotg->dev, "Host Global Registers\n"); in dwc2_dump_host_registers()
2176 addr = hsotg->regs + HCFG; in dwc2_dump_host_registers()
2177 dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
2179 addr = hsotg->regs + HFIR; in dwc2_dump_host_registers()
2180 dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
2182 addr = hsotg->regs + HFNUM; in dwc2_dump_host_registers()
2183 dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
2185 addr = hsotg->regs + HPTXSTS; in dwc2_dump_host_registers()
2186 dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
2188 addr = hsotg->regs + HAINT; in dwc2_dump_host_registers()
2189 dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
2191 addr = hsotg->regs + HAINTMSK; in dwc2_dump_host_registers()
2192 dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
2194 if (hsotg->core_params->dma_desc_enable > 0) { in dwc2_dump_host_registers()
2195 addr = hsotg->regs + HFLBADDR; in dwc2_dump_host_registers()
2196 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
2200 addr = hsotg->regs + HPRT0; in dwc2_dump_host_registers()
2201 dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
2204 for (i = 0; i < hsotg->core_params->host_channels; i++) { in dwc2_dump_host_registers()
2205 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i); in dwc2_dump_host_registers()
2206 addr = hsotg->regs + HCCHAR(i); in dwc2_dump_host_registers()
2207 dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
2209 addr = hsotg->regs + HCSPLT(i); in dwc2_dump_host_registers()
2210 dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
2212 addr = hsotg->regs + HCINT(i); in dwc2_dump_host_registers()
2213 dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
2215 addr = hsotg->regs + HCINTMSK(i); in dwc2_dump_host_registers()
2216 dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
2218 addr = hsotg->regs + HCTSIZ(i); in dwc2_dump_host_registers()
2219 dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
2221 addr = hsotg->regs + HCDMA(i); in dwc2_dump_host_registers()
2222 dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
2224 if (hsotg->core_params->dma_desc_enable > 0) { in dwc2_dump_host_registers()
2225 addr = hsotg->regs + HCDMAB(i); in dwc2_dump_host_registers()
2226 dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
2241 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg) in dwc2_dump_global_registers() argument
2246 dev_dbg(hsotg->dev, "Core Global Registers\n"); in dwc2_dump_global_registers()
2247 addr = hsotg->regs + GOTGCTL; in dwc2_dump_global_registers()
2248 dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2250 addr = hsotg->regs + GOTGINT; in dwc2_dump_global_registers()
2251 dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2253 addr = hsotg->regs + GAHBCFG; in dwc2_dump_global_registers()
2254 dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2256 addr = hsotg->regs + GUSBCFG; in dwc2_dump_global_registers()
2257 dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2259 addr = hsotg->regs + GRSTCTL; in dwc2_dump_global_registers()
2260 dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2262 addr = hsotg->regs + GINTSTS; in dwc2_dump_global_registers()
2263 dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2265 addr = hsotg->regs + GINTMSK; in dwc2_dump_global_registers()
2266 dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2268 addr = hsotg->regs + GRXSTSR; in dwc2_dump_global_registers()
2269 dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2271 addr = hsotg->regs + GRXFSIZ; in dwc2_dump_global_registers()
2272 dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2274 addr = hsotg->regs + GNPTXFSIZ; in dwc2_dump_global_registers()
2275 dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2277 addr = hsotg->regs + GNPTXSTS; in dwc2_dump_global_registers()
2278 dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2280 addr = hsotg->regs + GI2CCTL; in dwc2_dump_global_registers()
2281 dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2283 addr = hsotg->regs + GPVNDCTL; in dwc2_dump_global_registers()
2284 dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2286 addr = hsotg->regs + GGPIO; in dwc2_dump_global_registers()
2287 dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2289 addr = hsotg->regs + GUID; in dwc2_dump_global_registers()
2290 dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2292 addr = hsotg->regs + GSNPSID; in dwc2_dump_global_registers()
2293 dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2295 addr = hsotg->regs + GHWCFG1; in dwc2_dump_global_registers()
2296 dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2298 addr = hsotg->regs + GHWCFG2; in dwc2_dump_global_registers()
2299 dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2301 addr = hsotg->regs + GHWCFG3; in dwc2_dump_global_registers()
2302 dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2304 addr = hsotg->regs + GHWCFG4; in dwc2_dump_global_registers()
2305 dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2307 addr = hsotg->regs + GLPMCFG; in dwc2_dump_global_registers()
2308 dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2310 addr = hsotg->regs + GPWRDN; in dwc2_dump_global_registers()
2311 dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2313 addr = hsotg->regs + GDFIFOCFG; in dwc2_dump_global_registers()
2314 dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2316 addr = hsotg->regs + HPTXFSIZ; in dwc2_dump_global_registers()
2317 dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2320 addr = hsotg->regs + PCGCTL; in dwc2_dump_global_registers()
2321 dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2332 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num) in dwc2_flush_tx_fifo() argument
2337 dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num); in dwc2_flush_tx_fifo()
2341 dwc2_writel(greset, hsotg->regs + GRSTCTL); in dwc2_flush_tx_fifo()
2344 greset = dwc2_readl(hsotg->regs + GRSTCTL); in dwc2_flush_tx_fifo()
2346 dev_warn(hsotg->dev, in dwc2_flush_tx_fifo()
2349 dwc2_readl(hsotg->regs + GNPTXSTS)); in dwc2_flush_tx_fifo()
2364 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg) in dwc2_flush_rx_fifo() argument
2369 dev_vdbg(hsotg->dev, "%s()\n", __func__); in dwc2_flush_rx_fifo()
2372 dwc2_writel(greset, hsotg->regs + GRSTCTL); in dwc2_flush_rx_fifo()
2375 greset = dwc2_readl(hsotg->regs + GRSTCTL); in dwc2_flush_rx_fifo()
2377 dev_warn(hsotg->dev, "%s() HANG! GRSTCTL=%0x\n", in dwc2_flush_rx_fifo()
2391 void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_otg_cap() argument
2397 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) in dwc2_set_param_otg_cap()
2401 switch (hsotg->hw_params.op_mode) { in dwc2_set_param_otg_cap()
2422 dev_err(hsotg->dev, in dwc2_set_param_otg_cap()
2425 switch (hsotg->hw_params.op_mode) { in dwc2_set_param_otg_cap()
2438 dev_dbg(hsotg->dev, "Setting otg_cap to %d\n", val); in dwc2_set_param_otg_cap()
2441 hsotg->core_params->otg_cap = val; in dwc2_set_param_otg_cap()
2444 void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_dma_enable() argument
2448 if (val > 0 && hsotg->hw_params.arch == GHWCFG2_SLAVE_ONLY_ARCH) in dwc2_set_param_dma_enable()
2455 dev_err(hsotg->dev, in dwc2_set_param_dma_enable()
2458 val = hsotg->hw_params.arch != GHWCFG2_SLAVE_ONLY_ARCH; in dwc2_set_param_dma_enable()
2459 dev_dbg(hsotg->dev, "Setting dma_enable to %d\n", val); in dwc2_set_param_dma_enable()
2462 hsotg->core_params->dma_enable = val; in dwc2_set_param_dma_enable()
2465 void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_dma_desc_enable() argument
2469 if (val > 0 && (hsotg->core_params->dma_enable <= 0 || in dwc2_set_param_dma_desc_enable()
2470 !hsotg->hw_params.dma_desc_enable)) in dwc2_set_param_dma_desc_enable()
2477 dev_err(hsotg->dev, in dwc2_set_param_dma_desc_enable()
2480 val = (hsotg->core_params->dma_enable > 0 && in dwc2_set_param_dma_desc_enable()
2481 hsotg->hw_params.dma_desc_enable); in dwc2_set_param_dma_desc_enable()
2482 dev_dbg(hsotg->dev, "Setting dma_desc_enable to %d\n", val); in dwc2_set_param_dma_desc_enable()
2485 hsotg->core_params->dma_desc_enable = val; in dwc2_set_param_dma_desc_enable()
2488 void dwc2_set_param_host_support_fs_ls_low_power(struct dwc2_hsotg *hsotg, in dwc2_set_param_host_support_fs_ls_low_power() argument
2493 dev_err(hsotg->dev, in dwc2_set_param_host_support_fs_ls_low_power()
2495 dev_err(hsotg->dev, in dwc2_set_param_host_support_fs_ls_low_power()
2499 dev_dbg(hsotg->dev, in dwc2_set_param_host_support_fs_ls_low_power()
2503 hsotg->core_params->host_support_fs_ls_low_power = val; in dwc2_set_param_host_support_fs_ls_low_power()
2506 void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_enable_dynamic_fifo() argument
2510 if (val > 0 && !hsotg->hw_params.enable_dynamic_fifo) in dwc2_set_param_enable_dynamic_fifo()
2517 dev_err(hsotg->dev, in dwc2_set_param_enable_dynamic_fifo()
2520 val = hsotg->hw_params.enable_dynamic_fifo; in dwc2_set_param_enable_dynamic_fifo()
2521 dev_dbg(hsotg->dev, "Setting enable_dynamic_fifo to %d\n", val); in dwc2_set_param_enable_dynamic_fifo()
2524 hsotg->core_params->enable_dynamic_fifo = val; in dwc2_set_param_enable_dynamic_fifo()
2527 void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_host_rx_fifo_size() argument
2531 if (val < 16 || val > hsotg->hw_params.host_rx_fifo_size) in dwc2_set_param_host_rx_fifo_size()
2536 dev_err(hsotg->dev, in dwc2_set_param_host_rx_fifo_size()
2539 val = hsotg->hw_params.host_rx_fifo_size; in dwc2_set_param_host_rx_fifo_size()
2540 dev_dbg(hsotg->dev, "Setting host_rx_fifo_size to %d\n", val); in dwc2_set_param_host_rx_fifo_size()
2543 hsotg->core_params->host_rx_fifo_size = val; in dwc2_set_param_host_rx_fifo_size()
2546 void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_host_nperio_tx_fifo_size() argument
2550 if (val < 16 || val > hsotg->hw_params.host_nperio_tx_fifo_size) in dwc2_set_param_host_nperio_tx_fifo_size()
2555 dev_err(hsotg->dev, in dwc2_set_param_host_nperio_tx_fifo_size()
2558 val = hsotg->hw_params.host_nperio_tx_fifo_size; in dwc2_set_param_host_nperio_tx_fifo_size()
2559 dev_dbg(hsotg->dev, "Setting host_nperio_tx_fifo_size to %d\n", in dwc2_set_param_host_nperio_tx_fifo_size()
2563 hsotg->core_params->host_nperio_tx_fifo_size = val; in dwc2_set_param_host_nperio_tx_fifo_size()
2566 void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_host_perio_tx_fifo_size() argument
2570 if (val < 16 || val > hsotg->hw_params.host_perio_tx_fifo_size) in dwc2_set_param_host_perio_tx_fifo_size()
2575 dev_err(hsotg->dev, in dwc2_set_param_host_perio_tx_fifo_size()
2578 val = hsotg->hw_params.host_perio_tx_fifo_size; in dwc2_set_param_host_perio_tx_fifo_size()
2579 dev_dbg(hsotg->dev, "Setting host_perio_tx_fifo_size to %d\n", in dwc2_set_param_host_perio_tx_fifo_size()
2583 hsotg->core_params->host_perio_tx_fifo_size = val; in dwc2_set_param_host_perio_tx_fifo_size()
2586 void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_max_transfer_size() argument
2590 if (val < 2047 || val > hsotg->hw_params.max_transfer_size) in dwc2_set_param_max_transfer_size()
2595 dev_err(hsotg->dev, in dwc2_set_param_max_transfer_size()
2598 val = hsotg->hw_params.max_transfer_size; in dwc2_set_param_max_transfer_size()
2599 dev_dbg(hsotg->dev, "Setting max_transfer_size to %d\n", val); in dwc2_set_param_max_transfer_size()
2602 hsotg->core_params->max_transfer_size = val; in dwc2_set_param_max_transfer_size()
2605 void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_max_packet_count() argument
2609 if (val < 15 || val > hsotg->hw_params.max_packet_count) in dwc2_set_param_max_packet_count()
2614 dev_err(hsotg->dev, in dwc2_set_param_max_packet_count()
2617 val = hsotg->hw_params.max_packet_count; in dwc2_set_param_max_packet_count()
2618 dev_dbg(hsotg->dev, "Setting max_packet_count to %d\n", val); in dwc2_set_param_max_packet_count()
2621 hsotg->core_params->max_packet_count = val; in dwc2_set_param_max_packet_count()
2624 void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_host_channels() argument
2628 if (val < 1 || val > hsotg->hw_params.host_channels) in dwc2_set_param_host_channels()
2633 dev_err(hsotg->dev, in dwc2_set_param_host_channels()
2636 val = hsotg->hw_params.host_channels; in dwc2_set_param_host_channels()
2637 dev_dbg(hsotg->dev, "Setting host_channels to %d\n", val); in dwc2_set_param_host_channels()
2640 hsotg->core_params->host_channels = val; in dwc2_set_param_host_channels()
2643 void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_phy_type() argument
2651 dev_err(hsotg->dev, "Wrong value for phy_type\n"); in dwc2_set_param_phy_type()
2652 dev_err(hsotg->dev, "phy_type must be 0, 1 or 2\n"); in dwc2_set_param_phy_type()
2658 hs_phy_type = hsotg->hw_params.hs_phy_type; in dwc2_set_param_phy_type()
2659 fs_phy_type = hsotg->hw_params.fs_phy_type; in dwc2_set_param_phy_type()
2674 dev_err(hsotg->dev, in dwc2_set_param_phy_type()
2685 dev_dbg(hsotg->dev, "Setting phy_type to %d\n", val); in dwc2_set_param_phy_type()
2688 hsotg->core_params->phy_type = val; in dwc2_set_param_phy_type()
2691 static int dwc2_get_param_phy_type(struct dwc2_hsotg *hsotg) in dwc2_get_param_phy_type() argument
2693 return hsotg->core_params->phy_type; in dwc2_get_param_phy_type()
2696 void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_speed() argument
2702 dev_err(hsotg->dev, "Wrong value for speed parameter\n"); in dwc2_set_param_speed()
2703 dev_err(hsotg->dev, "max_speed parameter must be 0 or 1\n"); in dwc2_set_param_speed()
2709 dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS) in dwc2_set_param_speed()
2714 dev_err(hsotg->dev, in dwc2_set_param_speed()
2717 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS ? in dwc2_set_param_speed()
2719 dev_dbg(hsotg->dev, "Setting speed to %d\n", val); in dwc2_set_param_speed()
2722 hsotg->core_params->speed = val; in dwc2_set_param_speed()
2725 void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_host_ls_low_power_phy_clk() argument
2732 dev_err(hsotg->dev, in dwc2_set_param_host_ls_low_power_phy_clk()
2734 dev_err(hsotg->dev, in dwc2_set_param_host_ls_low_power_phy_clk()
2741 dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS) in dwc2_set_param_host_ls_low_power_phy_clk()
2746 dev_err(hsotg->dev, in dwc2_set_param_host_ls_low_power_phy_clk()
2749 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS in dwc2_set_param_host_ls_low_power_phy_clk()
2752 dev_dbg(hsotg->dev, "Setting host_ls_low_power_phy_clk to %d\n", in dwc2_set_param_host_ls_low_power_phy_clk()
2756 hsotg->core_params->host_ls_low_power_phy_clk = val; in dwc2_set_param_host_ls_low_power_phy_clk()
2759 void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_phy_ulpi_ddr() argument
2763 dev_err(hsotg->dev, "Wrong value for phy_ulpi_ddr\n"); in dwc2_set_param_phy_ulpi_ddr()
2764 dev_err(hsotg->dev, "phy_upli_ddr must be 0 or 1\n"); in dwc2_set_param_phy_ulpi_ddr()
2767 dev_dbg(hsotg->dev, "Setting phy_upli_ddr to %d\n", val); in dwc2_set_param_phy_ulpi_ddr()
2770 hsotg->core_params->phy_ulpi_ddr = val; in dwc2_set_param_phy_ulpi_ddr()
2773 void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_phy_ulpi_ext_vbus() argument
2777 dev_err(hsotg->dev, in dwc2_set_param_phy_ulpi_ext_vbus()
2779 dev_err(hsotg->dev, in dwc2_set_param_phy_ulpi_ext_vbus()
2783 dev_dbg(hsotg->dev, "Setting phy_ulpi_ext_vbus to %d\n", val); in dwc2_set_param_phy_ulpi_ext_vbus()
2786 hsotg->core_params->phy_ulpi_ext_vbus = val; in dwc2_set_param_phy_ulpi_ext_vbus()
2789 void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_phy_utmi_width() argument
2793 switch (hsotg->hw_params.utmi_phy_data_width) { in dwc2_set_param_phy_utmi_width()
2807 dev_err(hsotg->dev, in dwc2_set_param_phy_utmi_width()
2811 val = (hsotg->hw_params.utmi_phy_data_width == in dwc2_set_param_phy_utmi_width()
2813 dev_dbg(hsotg->dev, "Setting phy_utmi_width to %d\n", val); in dwc2_set_param_phy_utmi_width()
2816 hsotg->core_params->phy_utmi_width = val; in dwc2_set_param_phy_utmi_width()
2819 void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_ulpi_fs_ls() argument
2823 dev_err(hsotg->dev, "Wrong value for ulpi_fs_ls\n"); in dwc2_set_param_ulpi_fs_ls()
2824 dev_err(hsotg->dev, "ulpi_fs_ls must be 0 or 1\n"); in dwc2_set_param_ulpi_fs_ls()
2827 dev_dbg(hsotg->dev, "Setting ulpi_fs_ls to %d\n", val); in dwc2_set_param_ulpi_fs_ls()
2830 hsotg->core_params->ulpi_fs_ls = val; in dwc2_set_param_ulpi_fs_ls()
2833 void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_ts_dline() argument
2837 dev_err(hsotg->dev, "Wrong value for ts_dline\n"); in dwc2_set_param_ts_dline()
2838 dev_err(hsotg->dev, "ts_dline must be 0 or 1\n"); in dwc2_set_param_ts_dline()
2841 dev_dbg(hsotg->dev, "Setting ts_dline to %d\n", val); in dwc2_set_param_ts_dline()
2844 hsotg->core_params->ts_dline = val; in dwc2_set_param_ts_dline()
2847 void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_i2c_enable() argument
2853 dev_err(hsotg->dev, "Wrong value for i2c_enable\n"); in dwc2_set_param_i2c_enable()
2854 dev_err(hsotg->dev, "i2c_enable must be 0 or 1\n"); in dwc2_set_param_i2c_enable()
2860 if (val == 1 && !(hsotg->hw_params.i2c_enable)) in dwc2_set_param_i2c_enable()
2865 dev_err(hsotg->dev, in dwc2_set_param_i2c_enable()
2868 val = hsotg->hw_params.i2c_enable; in dwc2_set_param_i2c_enable()
2869 dev_dbg(hsotg->dev, "Setting i2c_enable to %d\n", val); in dwc2_set_param_i2c_enable()
2872 hsotg->core_params->i2c_enable = val; in dwc2_set_param_i2c_enable()
2875 void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_en_multiple_tx_fifo() argument
2881 dev_err(hsotg->dev, in dwc2_set_param_en_multiple_tx_fifo()
2883 dev_err(hsotg->dev, in dwc2_set_param_en_multiple_tx_fifo()
2889 if (val == 1 && !hsotg->hw_params.en_multiple_tx_fifo) in dwc2_set_param_en_multiple_tx_fifo()
2894 dev_err(hsotg->dev, in dwc2_set_param_en_multiple_tx_fifo()
2897 val = hsotg->hw_params.en_multiple_tx_fifo; in dwc2_set_param_en_multiple_tx_fifo()
2898 dev_dbg(hsotg->dev, "Setting en_multiple_tx_fifo to %d\n", val); in dwc2_set_param_en_multiple_tx_fifo()
2901 hsotg->core_params->en_multiple_tx_fifo = val; in dwc2_set_param_en_multiple_tx_fifo()
2904 void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_reload_ctl() argument
2910 dev_err(hsotg->dev, in dwc2_set_param_reload_ctl()
2912 dev_err(hsotg->dev, "reload_ctl must be 0 or 1\n"); in dwc2_set_param_reload_ctl()
2917 if (val == 1 && hsotg->hw_params.snpsid < DWC2_CORE_REV_2_92a) in dwc2_set_param_reload_ctl()
2922 dev_err(hsotg->dev, in dwc2_set_param_reload_ctl()
2925 val = hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_92a; in dwc2_set_param_reload_ctl()
2926 dev_dbg(hsotg->dev, "Setting reload_ctl to %d\n", val); in dwc2_set_param_reload_ctl()
2929 hsotg->core_params->reload_ctl = val; in dwc2_set_param_reload_ctl()
2932 void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_ahbcfg() argument
2935 hsotg->core_params->ahbcfg = val; in dwc2_set_param_ahbcfg()
2937 hsotg->core_params->ahbcfg = GAHBCFG_HBSTLEN_INCR4 << in dwc2_set_param_ahbcfg()
2941 void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_otg_ver() argument
2945 dev_err(hsotg->dev, in dwc2_set_param_otg_ver()
2947 dev_err(hsotg->dev, in dwc2_set_param_otg_ver()
2951 dev_dbg(hsotg->dev, "Setting otg_ver to %d\n", val); in dwc2_set_param_otg_ver()
2954 hsotg->core_params->otg_ver = val; in dwc2_set_param_otg_ver()
2957 static void dwc2_set_param_uframe_sched(struct dwc2_hsotg *hsotg, int val) in dwc2_set_param_uframe_sched() argument
2961 dev_err(hsotg->dev, in dwc2_set_param_uframe_sched()
2964 dev_err(hsotg->dev, "uframe_sched must be 0 or 1\n"); in dwc2_set_param_uframe_sched()
2967 dev_dbg(hsotg->dev, "Setting uframe_sched to %d\n", val); in dwc2_set_param_uframe_sched()
2970 hsotg->core_params->uframe_sched = val; in dwc2_set_param_uframe_sched()
2973 static void dwc2_set_param_external_id_pin_ctl(struct dwc2_hsotg *hsotg, in dwc2_set_param_external_id_pin_ctl() argument
2978 dev_err(hsotg->dev, in dwc2_set_param_external_id_pin_ctl()
2981 dev_err(hsotg->dev, "external_id_pin_ctl must be 0 or 1\n"); in dwc2_set_param_external_id_pin_ctl()
2984 dev_dbg(hsotg->dev, "Setting external_id_pin_ctl to %d\n", val); in dwc2_set_param_external_id_pin_ctl()
2987 hsotg->core_params->external_id_pin_ctl = val; in dwc2_set_param_external_id_pin_ctl()
2990 static void dwc2_set_param_hibernation(struct dwc2_hsotg *hsotg, in dwc2_set_param_hibernation() argument
2995 dev_err(hsotg->dev, in dwc2_set_param_hibernation()
2998 dev_err(hsotg->dev, "hibernation must be 0 or 1\n"); in dwc2_set_param_hibernation()
3001 dev_dbg(hsotg->dev, "Setting hibernation to %d\n", val); in dwc2_set_param_hibernation()
3004 hsotg->core_params->hibernation = val; in dwc2_set_param_hibernation()
3011 void dwc2_set_parameters(struct dwc2_hsotg *hsotg, in dwc2_set_parameters() argument
3014 dev_dbg(hsotg->dev, "%s()\n", __func__); in dwc2_set_parameters()
3016 dwc2_set_param_otg_cap(hsotg, params->otg_cap); in dwc2_set_parameters()
3017 dwc2_set_param_dma_enable(hsotg, params->dma_enable); in dwc2_set_parameters()
3018 dwc2_set_param_dma_desc_enable(hsotg, params->dma_desc_enable); in dwc2_set_parameters()
3019 dwc2_set_param_host_support_fs_ls_low_power(hsotg, in dwc2_set_parameters()
3021 dwc2_set_param_enable_dynamic_fifo(hsotg, in dwc2_set_parameters()
3023 dwc2_set_param_host_rx_fifo_size(hsotg, in dwc2_set_parameters()
3025 dwc2_set_param_host_nperio_tx_fifo_size(hsotg, in dwc2_set_parameters()
3027 dwc2_set_param_host_perio_tx_fifo_size(hsotg, in dwc2_set_parameters()
3029 dwc2_set_param_max_transfer_size(hsotg, in dwc2_set_parameters()
3031 dwc2_set_param_max_packet_count(hsotg, in dwc2_set_parameters()
3033 dwc2_set_param_host_channels(hsotg, params->host_channels); in dwc2_set_parameters()
3034 dwc2_set_param_phy_type(hsotg, params->phy_type); in dwc2_set_parameters()
3035 dwc2_set_param_speed(hsotg, params->speed); in dwc2_set_parameters()
3036 dwc2_set_param_host_ls_low_power_phy_clk(hsotg, in dwc2_set_parameters()
3038 dwc2_set_param_phy_ulpi_ddr(hsotg, params->phy_ulpi_ddr); in dwc2_set_parameters()
3039 dwc2_set_param_phy_ulpi_ext_vbus(hsotg, in dwc2_set_parameters()
3041 dwc2_set_param_phy_utmi_width(hsotg, params->phy_utmi_width); in dwc2_set_parameters()
3042 dwc2_set_param_ulpi_fs_ls(hsotg, params->ulpi_fs_ls); in dwc2_set_parameters()
3043 dwc2_set_param_ts_dline(hsotg, params->ts_dline); in dwc2_set_parameters()
3044 dwc2_set_param_i2c_enable(hsotg, params->i2c_enable); in dwc2_set_parameters()
3045 dwc2_set_param_en_multiple_tx_fifo(hsotg, in dwc2_set_parameters()
3047 dwc2_set_param_reload_ctl(hsotg, params->reload_ctl); in dwc2_set_parameters()
3048 dwc2_set_param_ahbcfg(hsotg, params->ahbcfg); in dwc2_set_parameters()
3049 dwc2_set_param_otg_ver(hsotg, params->otg_ver); in dwc2_set_parameters()
3050 dwc2_set_param_uframe_sched(hsotg, params->uframe_sched); in dwc2_set_parameters()
3051 dwc2_set_param_external_id_pin_ctl(hsotg, params->external_id_pin_ctl); in dwc2_set_parameters()
3052 dwc2_set_param_hibernation(hsotg, params->hibernation); in dwc2_set_parameters()
3059 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) in dwc2_get_hwparams() argument
3061 struct dwc2_hw_params *hw = &hsotg->hw_params; in dwc2_get_hwparams()
3073 hw->snpsid = dwc2_readl(hsotg->regs + GSNPSID); in dwc2_get_hwparams()
3076 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n", in dwc2_get_hwparams()
3081 dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n", in dwc2_get_hwparams()
3085 hwcfg1 = dwc2_readl(hsotg->regs + GHWCFG1); in dwc2_get_hwparams()
3086 hwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2); in dwc2_get_hwparams()
3087 hwcfg3 = dwc2_readl(hsotg->regs + GHWCFG3); in dwc2_get_hwparams()
3088 hwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4); in dwc2_get_hwparams()
3089 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); in dwc2_get_hwparams()
3091 dev_dbg(hsotg->dev, "hwcfg1=%08x\n", hwcfg1); in dwc2_get_hwparams()
3092 dev_dbg(hsotg->dev, "hwcfg2=%08x\n", hwcfg2); in dwc2_get_hwparams()
3093 dev_dbg(hsotg->dev, "hwcfg3=%08x\n", hwcfg3); in dwc2_get_hwparams()
3094 dev_dbg(hsotg->dev, "hwcfg4=%08x\n", hwcfg4); in dwc2_get_hwparams()
3095 dev_dbg(hsotg->dev, "grxfsiz=%08x\n", grxfsiz); in dwc2_get_hwparams()
3098 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); in dwc2_get_hwparams()
3100 dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG); in dwc2_get_hwparams()
3103 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); in dwc2_get_hwparams()
3104 hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ); in dwc2_get_hwparams()
3105 dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz); in dwc2_get_hwparams()
3106 dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz); in dwc2_get_hwparams()
3107 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); in dwc2_get_hwparams()
3109 dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG); in dwc2_get_hwparams()
3171 dev_dbg(hsotg->dev, "Detected values from hardware:\n"); in dwc2_get_hwparams()
3172 dev_dbg(hsotg->dev, " op_mode=%d\n", in dwc2_get_hwparams()
3174 dev_dbg(hsotg->dev, " arch=%d\n", in dwc2_get_hwparams()
3176 dev_dbg(hsotg->dev, " dma_desc_enable=%d\n", in dwc2_get_hwparams()
3178 dev_dbg(hsotg->dev, " power_optimized=%d\n", in dwc2_get_hwparams()
3180 dev_dbg(hsotg->dev, " i2c_enable=%d\n", in dwc2_get_hwparams()
3182 dev_dbg(hsotg->dev, " hs_phy_type=%d\n", in dwc2_get_hwparams()
3184 dev_dbg(hsotg->dev, " fs_phy_type=%d\n", in dwc2_get_hwparams()
3186 dev_dbg(hsotg->dev, " utmi_phy_data_width=%d\n", in dwc2_get_hwparams()
3188 dev_dbg(hsotg->dev, " num_dev_ep=%d\n", in dwc2_get_hwparams()
3190 dev_dbg(hsotg->dev, " num_dev_perio_in_ep=%d\n", in dwc2_get_hwparams()
3192 dev_dbg(hsotg->dev, " host_channels=%d\n", in dwc2_get_hwparams()
3194 dev_dbg(hsotg->dev, " max_transfer_size=%d\n", in dwc2_get_hwparams()
3196 dev_dbg(hsotg->dev, " max_packet_count=%d\n", in dwc2_get_hwparams()
3198 dev_dbg(hsotg->dev, " nperio_tx_q_depth=0x%0x\n", in dwc2_get_hwparams()
3200 dev_dbg(hsotg->dev, " host_perio_tx_q_depth=0x%0x\n", in dwc2_get_hwparams()
3202 dev_dbg(hsotg->dev, " dev_token_q_depth=0x%0x\n", in dwc2_get_hwparams()
3204 dev_dbg(hsotg->dev, " enable_dynamic_fifo=%d\n", in dwc2_get_hwparams()
3206 dev_dbg(hsotg->dev, " en_multiple_tx_fifo=%d\n", in dwc2_get_hwparams()
3208 dev_dbg(hsotg->dev, " total_fifo_size=%d\n", in dwc2_get_hwparams()
3210 dev_dbg(hsotg->dev, " host_rx_fifo_size=%d\n", in dwc2_get_hwparams()
3212 dev_dbg(hsotg->dev, " host_nperio_tx_fifo_size=%d\n", in dwc2_get_hwparams()
3214 dev_dbg(hsotg->dev, " host_perio_tx_fifo_size=%d\n", in dwc2_get_hwparams()
3216 dev_dbg(hsotg->dev, "\n"); in dwc2_get_hwparams()
3237 u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg) in dwc2_get_otg_version() argument
3239 return hsotg->core_params->otg_ver == 1 ? 0x0200 : 0x0103; in dwc2_get_otg_version()
3242 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg) in dwc2_is_controller_alive() argument
3244 if (dwc2_readl(hsotg->regs + GSNPSID) == 0xffffffff) in dwc2_is_controller_alive()
3256 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg) in dwc2_enable_global_interrupts() argument
3258 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); in dwc2_enable_global_interrupts()
3261 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); in dwc2_enable_global_interrupts()
3270 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg) in dwc2_disable_global_interrupts() argument
3272 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); in dwc2_disable_global_interrupts()
3275 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); in dwc2_disable_global_interrupts()