Lines Matching refs:dev_dbg
72 dev_dbg(hsotg->dev, "%s\n", __func__); in dwc2_backup_host_registers()
100 dev_dbg(hsotg->dev, "%s\n", __func__); in dwc2_restore_host_registers()
145 dev_dbg(hsotg->dev, "%s\n", __func__); in dwc2_backup_device_registers()
198 dev_dbg(hsotg->dev, "%s\n", __func__); in dwc2_restore_device_registers()
284 dev_dbg(hsotg->dev, "%s\n", __func__); in dwc2_restore_global_registers()
473 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val); in dwc2_init_fs_ls_pclk_sel()
555 dev_dbg(hsotg->dev, "FS PHY selected\n"); in dwc2_fs_phy_init()
578 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n"); in dwc2_fs_phy_init()
616 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n"); in dwc2_hs_phy_init()
624 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n"); in dwc2_hs_phy_init()
668 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n"); in dwc2_phy_init()
693 dev_dbg(hsotg->dev, "Internal DMA Mode\n"); in dwc2_gahbcfg_init()
703 dev_dbg(hsotg->dev, "Slave Only Mode\n"); in dwc2_gahbcfg_init()
707 dev_dbg(hsotg->dev, "dma_enable:%d dma_desc_enable:%d\n", in dwc2_gahbcfg_init()
713 dev_dbg(hsotg->dev, "Using Descriptor DMA mode\n"); in dwc2_gahbcfg_init()
715 dev_dbg(hsotg->dev, "Using Buffer DMA mode\n"); in dwc2_gahbcfg_init()
717 dev_dbg(hsotg->dev, "Using Slave mode\n"); in dwc2_gahbcfg_init()
777 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); in dwc2_core_init()
823 dev_dbg(hsotg->dev, "OTG VER PARAM: %d\n", hsotg->core_params->otg_ver); in dwc2_core_init()
836 dev_dbg(hsotg->dev, "Host Mode\n"); in dwc2_core_init()
839 dev_dbg(hsotg->dev, "Device Mode\n"); in dwc2_core_init()
855 dev_dbg(hsotg->dev, "%s()\n", __func__); in dwc2_enable_host_interrupts()
963 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz); in dwc2_config_fifos()
968 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n", in dwc2_config_fifos()
972 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n", in dwc2_config_fifos()
979 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n", in dwc2_config_fifos()
983 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n", in dwc2_config_fifos()
991 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n", in dwc2_config_fifos()
1025 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); in dwc2_core_host_init()
1108 dev_dbg(hsotg->dev, "%s: Halt channel %d\n", in dwc2_core_host_init()
1124 dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state); in dwc2_core_host_init()
1128 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n", in dwc2_core_host_init()
1485 dev_dbg(hsotg->dev, "desc DMA enabled\n"); in dwc2_hc_halt()
2175 dev_dbg(hsotg->dev, "Host Global Registers\n"); in dwc2_dump_host_registers()
2177 dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
2180 dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
2183 dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
2186 dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
2189 dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
2192 dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
2196 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
2201 dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
2205 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i); in dwc2_dump_host_registers()
2207 dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
2210 dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
2213 dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
2216 dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
2219 dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
2222 dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
2226 dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
2246 dev_dbg(hsotg->dev, "Core Global Registers\n"); in dwc2_dump_global_registers()
2248 dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2251 dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2254 dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2257 dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2260 dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2263 dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2266 dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2269 dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2272 dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2275 dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2278 dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2281 dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2284 dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2287 dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2290 dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2293 dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2296 dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2299 dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2302 dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2305 dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2308 dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2311 dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2314 dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2317 dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2321 dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
2438 dev_dbg(hsotg->dev, "Setting otg_cap to %d\n", val); in dwc2_set_param_otg_cap()
2459 dev_dbg(hsotg->dev, "Setting dma_enable to %d\n", val); in dwc2_set_param_dma_enable()
2482 dev_dbg(hsotg->dev, "Setting dma_desc_enable to %d\n", val); in dwc2_set_param_dma_desc_enable()
2499 dev_dbg(hsotg->dev, in dwc2_set_param_host_support_fs_ls_low_power()
2521 dev_dbg(hsotg->dev, "Setting enable_dynamic_fifo to %d\n", val); in dwc2_set_param_enable_dynamic_fifo()
2540 dev_dbg(hsotg->dev, "Setting host_rx_fifo_size to %d\n", val); in dwc2_set_param_host_rx_fifo_size()
2559 dev_dbg(hsotg->dev, "Setting host_nperio_tx_fifo_size to %d\n", in dwc2_set_param_host_nperio_tx_fifo_size()
2579 dev_dbg(hsotg->dev, "Setting host_perio_tx_fifo_size to %d\n", in dwc2_set_param_host_perio_tx_fifo_size()
2599 dev_dbg(hsotg->dev, "Setting max_transfer_size to %d\n", val); in dwc2_set_param_max_transfer_size()
2618 dev_dbg(hsotg->dev, "Setting max_packet_count to %d\n", val); in dwc2_set_param_max_packet_count()
2637 dev_dbg(hsotg->dev, "Setting host_channels to %d\n", val); in dwc2_set_param_host_channels()
2685 dev_dbg(hsotg->dev, "Setting phy_type to %d\n", val); in dwc2_set_param_phy_type()
2719 dev_dbg(hsotg->dev, "Setting speed to %d\n", val); in dwc2_set_param_speed()
2752 dev_dbg(hsotg->dev, "Setting host_ls_low_power_phy_clk to %d\n", in dwc2_set_param_host_ls_low_power_phy_clk()
2767 dev_dbg(hsotg->dev, "Setting phy_upli_ddr to %d\n", val); in dwc2_set_param_phy_ulpi_ddr()
2783 dev_dbg(hsotg->dev, "Setting phy_ulpi_ext_vbus to %d\n", val); in dwc2_set_param_phy_ulpi_ext_vbus()
2813 dev_dbg(hsotg->dev, "Setting phy_utmi_width to %d\n", val); in dwc2_set_param_phy_utmi_width()
2827 dev_dbg(hsotg->dev, "Setting ulpi_fs_ls to %d\n", val); in dwc2_set_param_ulpi_fs_ls()
2841 dev_dbg(hsotg->dev, "Setting ts_dline to %d\n", val); in dwc2_set_param_ts_dline()
2869 dev_dbg(hsotg->dev, "Setting i2c_enable to %d\n", val); in dwc2_set_param_i2c_enable()
2898 dev_dbg(hsotg->dev, "Setting en_multiple_tx_fifo to %d\n", val); in dwc2_set_param_en_multiple_tx_fifo()
2926 dev_dbg(hsotg->dev, "Setting reload_ctl to %d\n", val); in dwc2_set_param_reload_ctl()
2951 dev_dbg(hsotg->dev, "Setting otg_ver to %d\n", val); in dwc2_set_param_otg_ver()
2967 dev_dbg(hsotg->dev, "Setting uframe_sched to %d\n", val); in dwc2_set_param_uframe_sched()
2984 dev_dbg(hsotg->dev, "Setting external_id_pin_ctl to %d\n", val); in dwc2_set_param_external_id_pin_ctl()
3001 dev_dbg(hsotg->dev, "Setting hibernation to %d\n", val); in dwc2_set_param_hibernation()
3014 dev_dbg(hsotg->dev, "%s()\n", __func__); in dwc2_set_parameters()
3081 dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n", in dwc2_get_hwparams()
3091 dev_dbg(hsotg->dev, "hwcfg1=%08x\n", hwcfg1); in dwc2_get_hwparams()
3092 dev_dbg(hsotg->dev, "hwcfg2=%08x\n", hwcfg2); in dwc2_get_hwparams()
3093 dev_dbg(hsotg->dev, "hwcfg3=%08x\n", hwcfg3); in dwc2_get_hwparams()
3094 dev_dbg(hsotg->dev, "hwcfg4=%08x\n", hwcfg4); in dwc2_get_hwparams()
3095 dev_dbg(hsotg->dev, "grxfsiz=%08x\n", grxfsiz); in dwc2_get_hwparams()
3105 dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz); in dwc2_get_hwparams()
3106 dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz); in dwc2_get_hwparams()
3171 dev_dbg(hsotg->dev, "Detected values from hardware:\n"); in dwc2_get_hwparams()
3172 dev_dbg(hsotg->dev, " op_mode=%d\n", in dwc2_get_hwparams()
3174 dev_dbg(hsotg->dev, " arch=%d\n", in dwc2_get_hwparams()
3176 dev_dbg(hsotg->dev, " dma_desc_enable=%d\n", in dwc2_get_hwparams()
3178 dev_dbg(hsotg->dev, " power_optimized=%d\n", in dwc2_get_hwparams()
3180 dev_dbg(hsotg->dev, " i2c_enable=%d\n", in dwc2_get_hwparams()
3182 dev_dbg(hsotg->dev, " hs_phy_type=%d\n", in dwc2_get_hwparams()
3184 dev_dbg(hsotg->dev, " fs_phy_type=%d\n", in dwc2_get_hwparams()
3186 dev_dbg(hsotg->dev, " utmi_phy_data_width=%d\n", in dwc2_get_hwparams()
3188 dev_dbg(hsotg->dev, " num_dev_ep=%d\n", in dwc2_get_hwparams()
3190 dev_dbg(hsotg->dev, " num_dev_perio_in_ep=%d\n", in dwc2_get_hwparams()
3192 dev_dbg(hsotg->dev, " host_channels=%d\n", in dwc2_get_hwparams()
3194 dev_dbg(hsotg->dev, " max_transfer_size=%d\n", in dwc2_get_hwparams()
3196 dev_dbg(hsotg->dev, " max_packet_count=%d\n", in dwc2_get_hwparams()
3198 dev_dbg(hsotg->dev, " nperio_tx_q_depth=0x%0x\n", in dwc2_get_hwparams()
3200 dev_dbg(hsotg->dev, " host_perio_tx_q_depth=0x%0x\n", in dwc2_get_hwparams()
3202 dev_dbg(hsotg->dev, " dev_token_q_depth=0x%0x\n", in dwc2_get_hwparams()
3204 dev_dbg(hsotg->dev, " enable_dynamic_fifo=%d\n", in dwc2_get_hwparams()
3206 dev_dbg(hsotg->dev, " en_multiple_tx_fifo=%d\n", in dwc2_get_hwparams()
3208 dev_dbg(hsotg->dev, " total_fifo_size=%d\n", in dwc2_get_hwparams()
3210 dev_dbg(hsotg->dev, " host_rx_fifo_size=%d\n", in dwc2_get_hwparams()
3212 dev_dbg(hsotg->dev, " host_nperio_tx_fifo_size=%d\n", in dwc2_get_hwparams()
3214 dev_dbg(hsotg->dev, " host_perio_tx_fifo_size=%d\n", in dwc2_get_hwparams()
3216 dev_dbg(hsotg->dev, "\n"); in dwc2_get_hwparams()