386 #define TXDMA 	0x20  macro
2228 	write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */  in isr_txeom()
2229 	write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */  in isr_txeom()
2230 	write_reg(info, TXDMA + DCMD, SWABORT);	/* reset/init DMA channel */  in isr_txeom()
2380 	write_reg(info, TXDMA + DIR, 0x00);	/* disable Tx DMA IRQs */  in isr_txdmaok()
2381 	write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */  in isr_txdmaok()
2382 	write_reg(info, TXDMA + DCMD, SWABORT);	/* reset/init DMA channel */  in isr_txdmaok()
2399 	unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;  in isr_txdmaerror()
2402 	write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));  in isr_txdmaerror()
2993 		write_reg(info, TXDMA + DSR, 0);		/* disable DMA channel */  in tx_abort()
2994 		write_reg(info, TXDMA + DCMD, SWABORT);	/* reset/init DMA channel */  in tx_abort()
4228 			write_reg(info, TXDMA + DSR, 0); 		/* disable DMA channel */  in tx_start()
4229 			write_reg(info, TXDMA + DCMD, SWABORT);	/* reset/init DMA channel */  in tx_start()
4232 			write_reg16(info, TXDMA + CDA,  in tx_start()
4236 			write_reg16(info, TXDMA + EDA,  in tx_start()
4245 			write_reg(info, TXDMA + DIR, 0x40);		/* enable Tx DMA interrupts (EOM) */  in tx_start()
4246 			write_reg(info, TXDMA + DSR, 0xf2);		/* clear Tx DMA IRQs, enable Tx DMA */  in tx_start()
4272 	write_reg(info, TXDMA + DSR, 0);		/* disable DMA channel */  in tx_stop()
4273 	write_reg(info, TXDMA + DCMD, SWABORT);	/* reset/init DMA channel */  in tx_stop()
4527 	write_reg(info, TXDMA + DIR, 0);  in hdlc_mode()
4669 	write_reg(info, TXDMA + DMR, 0x14);  in hdlc_mode()
4677 	write_reg(info, TXDMA + CPB,  in hdlc_mode()