1517 	unsigned char RegValue;  in set_break()  local
1529 	RegValue = read_reg(info, CTL);  in set_break()
1531 		RegValue |= BIT3;  in set_break()
1533 		RegValue &= ~BIT3;  in set_break()
1534 	write_reg(info, CTL, RegValue);  in set_break()
4379   	unsigned char RegValue;  in async_mode()  local
4394 	RegValue = 0x00;  in async_mode()
4396 		RegValue |= BIT1;  in async_mode()
4397 	write_reg(info, MD0, RegValue);  in async_mode()
4408 	RegValue = 0x40;  in async_mode()
4410 	case 7: RegValue |= BIT4 + BIT2; break;  in async_mode()
4411 	case 6: RegValue |= BIT5 + BIT3; break;  in async_mode()
4412 	case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;  in async_mode()
4415 		RegValue |= BIT1;  in async_mode()
4417 			RegValue |= BIT0;  in async_mode()
4419 	write_reg(info, MD1, RegValue);  in async_mode()
4428 	RegValue = 0x00;  in async_mode()
4430 		RegValue |= (BIT1 + BIT0);  in async_mode()
4431 	write_reg(info, MD2, RegValue);  in async_mode()
4439 	RegValue=BIT6;  in async_mode()
4440 	write_reg(info, RXS, RegValue);  in async_mode()
4448 	RegValue=BIT6;  in async_mode()
4449 	write_reg(info, TXS, RegValue);  in async_mode()
4493 	RegValue = 0x10;  in async_mode()
4495 		RegValue |= 0x01;  in async_mode()
4496 	write_reg(info, CTL, RegValue);  in async_mode()
4517 	unsigned char RegValue;  in hdlc_mode()  local
4541 	RegValue = 0x81;  in hdlc_mode()
4543 		RegValue |= BIT4;  in hdlc_mode()
4545 		RegValue |= BIT4;  in hdlc_mode()
4547 		RegValue |= BIT2 + BIT1;  in hdlc_mode()
4548 	write_reg(info, MD0, RegValue);  in hdlc_mode()
4559 	RegValue = 0x00;  in hdlc_mode()
4560 	write_reg(info, MD1, RegValue);  in hdlc_mode()
4572 	RegValue = 0x00;  in hdlc_mode()
4574 	case HDLC_ENCODING_NRZI:	  RegValue |= BIT5; break;  in hdlc_mode()
4575 	case HDLC_ENCODING_BIPHASE_MARK:  RegValue |= BIT7 + BIT5; break; /* aka FM1 */  in hdlc_mode()
4576 	case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */  in hdlc_mode()
4577 	case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break; 	/* aka Manchester */  in hdlc_mode()
4586 		RegValue |= BIT3;  in hdlc_mode()
4591 		RegValue |= BIT4;  in hdlc_mode()
4593 	write_reg(info, MD2, RegValue);  in hdlc_mode()
4602 	RegValue=0;  in hdlc_mode()
4604 		RegValue |= BIT6;  in hdlc_mode()
4606 		RegValue |= BIT6 + BIT5;  in hdlc_mode()
4607 	write_reg(info, RXS, RegValue);  in hdlc_mode()
4615 	RegValue=0;  in hdlc_mode()
4617 		RegValue |= BIT6;  in hdlc_mode()
4619 		RegValue |= BIT6 + BIT5;  in hdlc_mode()
4620 	write_reg(info, TXS, RegValue);  in hdlc_mode()
4698 	RegValue = 0x10;  in hdlc_mode()
4700 		RegValue |= 0x01;  in hdlc_mode()
4701 	write_reg(info, CTL, RegValue);  in hdlc_mode()
4719 	unsigned char RegValue = 0xff;  in tx_set_idle()  local
4723 	case HDLC_TXIDLE_FLAGS:			RegValue = 0x7e; break;  in tx_set_idle()
4724 	case HDLC_TXIDLE_ALT_ZEROS_ONES:	RegValue = 0xaa; break;  in tx_set_idle()
4725 	case HDLC_TXIDLE_ZEROS:			RegValue = 0x00; break;  in tx_set_idle()
4726 	case HDLC_TXIDLE_ONES:			RegValue = 0xff; break;  in tx_set_idle()
4727 	case HDLC_TXIDLE_ALT_MARK_SPACE:	RegValue = 0xaa; break;  in tx_set_idle()
4728 	case HDLC_TXIDLE_SPACE:			RegValue = 0x00; break;  in tx_set_idle()
4729 	case HDLC_TXIDLE_MARK:			RegValue = 0xff; break;  in tx_set_idle()
4732 	write_reg(info, IDL, RegValue);  in tx_set_idle()
4768 	unsigned char RegValue;  in set_signals()  local
4771 	RegValue = read_reg(info, CTL);  in set_signals()
4773 		RegValue &= ~BIT0;  in set_signals()
4775 		RegValue |= BIT0;  in set_signals()
4776 	write_reg(info, CTL, RegValue);  in set_signals()