428 	wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
430 	wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
435 static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
1418 	wr_reg16(info, TCR, value);  in set_break()
2158 	wr_reg16(info, SSR, status); /* clear pending */  in isr_serial()
2298 		wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */  in isr_txeom()
2299 		wr_reg16(info, TCR, val); /* clear reset bit */  in isr_txeom()
2742 			wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);  in rx_enable()
2795 			wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));  in wait_mgsl_event()
2858 			wr_reg16(info, SCR,  in wait_mgsl_event()
2894 	wr_reg16(info, TCR, val);  in set_interface()
3879 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)  in wr_reg16()  function
3931 	wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));  in enable_loopback()
3970 		wr_reg16(info, BDR, (unsigned short)div);  in set_rate()
3980 	wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */  in rx_stop()
3981 	wr_reg16(info, RCR, val);                  /* clear reset bit */  in rx_stop()
3986 	wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);  in rx_stop()
4001 	wr_reg16(info, SSR, IRQ_RXOVER);  in rx_start()
4005 	wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */  in rx_start()
4006 	wr_reg16(info, RCR, val);                  /* clear reset bit */  in rx_start()
4013 		wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));  in rx_start()
4021 		wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));  in rx_start()
4037 	wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));  in rx_start()
4046 		wr_reg16(info, TCR,  in tx_start()
4067 			wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));  in tx_start()
4072 			wr_reg16(info, SSR, IRQ_TXIDLE);  in tx_start()
4091 	wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */  in tx_stop()
4096 	wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));  in tx_stop()
4177 	wr_reg16(info, TCR, val);  in async_mode()
4214 	wr_reg16(info, RCR, val);  in async_mode()
4260 	wr_reg16(info, SCR, val);  in async_mode()
4339 	wr_reg16(info, TCR, val);  in sync_mode()
4402 	wr_reg16(info, RCR, val);  in sync_mode()
4453 		wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));  in sync_mode()
4484 	wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);  in sync_mode()
4511 	wr_reg16(info, TCR, tcr);  in tx_set_idle()
4972 		wr_reg16(info, TIR, patterns[i]);  in register_test()
4973 		wr_reg16(info, BDR, patterns[(i+1)%count]);  in register_test()
5000 	wr_reg16(info, TCR,  in irq_test()
5004 	wr_reg16(info, TDR, 0);  in irq_test()