Lines Matching refs:BIT4
385 #define MASK_OVERRUN BIT4
423 #define IRQ_RI BIT4
2228 if (status & (BIT5 + BIT4)) { in isr_rdma()
2253 if (status & (BIT5 + BIT4 + BIT3)) { in isr_tdma()
4166 case 6: val |= BIT4; break; in async_mode()
4168 case 8: val |= BIT5 + BIT4; break; in async_mode()
4206 case 6: val |= BIT4; break; in async_mode()
4208 case 8: val |= BIT5 + BIT4; break; in async_mode()
4332 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break; in sync_mode()
4333 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break; in sync_mode()
4431 val |= BIT4; /* 100, rxclk = DPLL */ in sync_mode()
4504 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4; in tx_set_idle()
4509 tcr &= ~(BIT5 + BIT4); in tx_set_idle()
4582 val |= BIT4; in msc_set_vcr()