Lines Matching refs:BIT0
215 …a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
222 #define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
383 #define MASK_FRAMING BIT0
425 #define IRQ_MASTER BIT0
1876 status = *(p + 1) & (BIT1 + BIT0); in rx_async()
1880 else if (status & BIT0) in rx_async()
1887 else if (status & BIT0) in rx_async()
2100 if (status & BIT0) { in ri_change()
3906 if (!(rd_reg32(info, RDCSR) & BIT0)) in rdma_reset()
3919 if (!(rd_reg32(info, TDCSR) & BIT0)) in tdma_reset()
4027 wr_reg32(info, RDCSR, (BIT2 + BIT0)); in rx_start()
4030 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0)); in rx_start()
4076 wr_reg32(info, TDCSR, BIT2 + BIT0); in tx_start()
4175 val |= BIT0; in async_mode()
4212 val |= BIT0; in async_mode()
4248 val = BIT15 + BIT14 + BIT0; in async_mode()
4337 val |= BIT0; in sync_mode()
4400 val |= BIT0; in sync_mode()
4436 val |= BIT1 + BIT0; in sync_mode()
4484 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0); in sync_mode()
4548 if (status & BIT0) in get_signals()
4590 val |= BIT0; in msc_set_vcr()
4712 if (framesize < (2 + crc_size) || status & BIT0) { in rx_get_frame()
4836 if (count && (rd_reg32(info, TDCSR) & BIT0)) in free_tbuf_count()
4879 if (reg_value & BIT0) in tbuf_bytes()