Lines Matching refs:usc_InDmaReg
640 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
643 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
665 static u16 usc_InDmaReg( struct mgsl_struct *info, u16 Port );
1602 status = usc_InDmaReg( info, RDMR ); in mgsl_isr_receive_dma()
1647 status = usc_InDmaReg( info, TDMR ); in mgsl_isr_transmit_dma()
1695 DmaVector = usc_InDmaReg(info, DIVR); in mgsl_interrupt()
3521 u16 Tdmr = usc_InDmaReg( info, TDMR ); in line_info()
3524 u16 Rdmr = usc_InDmaReg( info, RDMR ); in line_info()
4565 static u16 usc_InDmaReg( struct mgsl_struct *info, u16 RegAddr ) in usc_InDmaReg() function
5142 usc_InDmaReg( info, RDMR ); /* clear pending receive DMA IRQ bits */ in usc_set_sdlc_mode()
5143 usc_InDmaReg( info, TDMR ); /* clear pending transmit DMA IRQ bits */ in usc_set_sdlc_mode()
5444 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) ); in usc_process_rxoverrun_sync()
5533 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) ); in usc_start_receiver()
5639 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT0) ); in usc_start_transmitter()
6968 (usc_InDmaReg( info, DIVR ) != 0) ){ in mgsl_register_test()
6989 (usc_InDmaReg( info, TBCR ) != BitPatterns[(i+5)%Patterncount]) ){ in mgsl_register_test()
7162 usc_InDmaReg( info, RDMR ); in mgsl_dma_test()
7185 status = usc_InDmaReg( info, RDMR ); in mgsl_dma_test()