1460 		outw( (inw(info->io_base + CCAR) & 0x0780) | (RDR+LSBONLY),  in mgsl_isr_receive_data()
4487 	outw( Cmd + info->loopback_bits, info->io_base + CCAR );  in usc_RTCmd()
4512 	outw( Cmd + info->mbre_bit, info->io_base );  in usc_DmaCmd()
4541 	outw( RegAddr + info->mbre_bit, info->io_base );  in usc_OutDmaReg()
4542 	outw( RegValue, info->io_base );  in usc_OutDmaReg()
4570 	outw( RegAddr + info->mbre_bit, info->io_base );  in usc_InDmaReg()
4594 	outw( RegAddr + info->loopback_bits, info->io_base + CCAR );  in usc_OutReg()
4595 	outw( RegValue, info->io_base + CCAR );  in usc_OutReg()
4619 	outw( RegAddr + info->loopback_bits, info->io_base + CCAR );  in usc_InReg()
5054 	outw( 0, info->io_base ); 			/* clear Master Bus Enable (DCAR) */  in usc_set_sdlc_mode()
5057 	outw( BIT8, info->io_base );			/* set Master Bus Enable (DCAR) */  in usc_set_sdlc_mode()
5247 		outw( 0x0300, info->io_base + CCAR );  in usc_enable_loopback()
5254 		outw( 0,info->io_base + CCAR );  in usc_enable_loopback()
5724 			outw( *((u16 *)TwoBytes), info->io_base + DATAREG);  in usc_load_txfifo()
5731 			outw( (inw( info->io_base + CCAR) & 0x0780) | (TDR+LSBONLY),  in usc_load_txfifo()
5736 				outw( info->x_char,info->io_base + CCAR );  in usc_load_txfifo()
5739 				outw( info->xmit_buf[info->xmit_tail++],info->io_base + CCAR );  in usc_load_txfifo()
5818 	outw( 0x000c,info->io_base + SDPIN );  in usc_reset()
5821 	outw( 0,info->io_base );  in usc_reset()
5822 	outw( 0,info->io_base + CCAR );  in usc_reset()
5877 	outw( 0, info->io_base ); 			/* clear Master Bus Enable (DCAR) */  in usc_set_async_mode()
6049 		outw(0x0300, info->io_base + CCAR);  in usc_set_async_mode()
6111 	outw(0,info->io_base + DATAREG);  in usc_loopback_frame()