260 	unsigned int io_base;		/* base I/O address of adapter */  member
1460 		outw( (inw(info->io_base + CCAR) & 0x0780) | (RDR+LSBONLY),  in mgsl_isr_receive_data()
1461 		      info->io_base + CCAR );  in mgsl_isr_receive_data()
1462 		DataByte = inb( info->io_base + CCAR );  in mgsl_isr_receive_data()
3454 			info->device_name, info->io_base, info->irq_level,  in line_info()
3458 			info->device_name, info->io_base,   in line_info()
3530 	u16 Ccar = inw( info->io_base + CCAR );  in line_info()
4058 	if (request_region(info->io_base,info->io_addr_size,"synclink") == NULL) {  in mgsl_claim_resources()
4060 			__FILE__,__LINE__,info->device_name, info->io_base);  in mgsl_claim_resources()
4159 		release_region(info->io_base,info->io_addr_size);  in mgsl_release_resources()
4236 			info->hw_version + 1, info->device_name, info->io_base, info->irq_level,  in mgsl_add_device()
4241 			info->device_name, info->io_base, info->irq_level, info->dma_level,  in mgsl_add_device()
4382 		info->io_base = (unsigned int)io[i];  in mgsl_enum_isa_devices()
4487 	outw( Cmd + info->loopback_bits, info->io_base + CCAR );  in usc_RTCmd()
4491 		inw( info->io_base + CCAR );  in usc_RTCmd()
4512 	outw( Cmd + info->mbre_bit, info->io_base );  in usc_DmaCmd()
4516 		inw( info->io_base );  in usc_DmaCmd()
4541 	outw( RegAddr + info->mbre_bit, info->io_base );  in usc_OutDmaReg()
4542 	outw( RegValue, info->io_base );  in usc_OutDmaReg()
4546 		inw( info->io_base );  in usc_OutDmaReg()
4570 	outw( RegAddr + info->mbre_bit, info->io_base );  in usc_InDmaReg()
4571 	return inw( info->io_base );  in usc_InDmaReg()
4594 	outw( RegAddr + info->loopback_bits, info->io_base + CCAR );  in usc_OutReg()
4595 	outw( RegValue, info->io_base + CCAR );  in usc_OutReg()
4599 		inw( info->io_base + CCAR );  in usc_OutReg()
4619 	outw( RegAddr + info->loopback_bits, info->io_base + CCAR );  in usc_InReg()
4620 	return inw( info->io_base + CCAR );  in usc_InReg()
5054 	outw( 0, info->io_base ); 			/* clear Master Bus Enable (DCAR) */  in usc_set_sdlc_mode()
5057 	outw( BIT8, info->io_base );			/* set Master Bus Enable (DCAR) */  in usc_set_sdlc_mode()
5247 		outw( 0x0300, info->io_base + CCAR );  in usc_enable_loopback()
5254 		outw( 0,info->io_base + CCAR );  in usc_enable_loopback()
5724 			outw( *((u16 *)TwoBytes), info->io_base + DATAREG);  in usc_load_txfifo()
5731 			outw( (inw( info->io_base + CCAR) & 0x0780) | (TDR+LSBONLY),  in usc_load_txfifo()
5732 				info->io_base + CCAR );  in usc_load_txfifo()
5736 				outw( info->x_char,info->io_base + CCAR );  in usc_load_txfifo()
5739 				outw( info->xmit_buf[info->xmit_tail++],info->io_base + CCAR );  in usc_load_txfifo()
5794 		outb( 0,info->io_base + 8 );  in usc_reset()
5818 	outw( 0x000c,info->io_base + SDPIN );  in usc_reset()
5821 	outw( 0,info->io_base );  in usc_reset()
5822 	outw( 0,info->io_base + CCAR );  in usc_reset()
5877 	outw( 0, info->io_base ); 			/* clear Master Bus Enable (DCAR) */  in usc_set_async_mode()
6049 		outw(0x0300, info->io_base + CCAR);  in usc_set_async_mode()
6111 	outw(0,info->io_base + DATAREG);  in usc_loopback_frame()
7361 			__FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );  in mgsl_adapter_test()
8020 	dev->base_addr = info->io_base;  in hdlcdev_init()
8080 	info->io_base = pci_resource_start(dev, 2);  in synclink_init_one()