Lines Matching refs:RegValue
4536 static void usc_OutDmaReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue ) in usc_OutDmaReg() argument
4542 outw( RegValue, info->io_base ); in usc_OutDmaReg()
4592 static void usc_OutReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue ) in usc_OutReg() argument
4595 outw( RegValue, info->io_base + CCAR ); in usc_OutReg()
4633 u16 RegValue; in usc_set_sdlc_mode() local
4646 RegValue=usc_InReg(info,TMDR); in usc_set_sdlc_mode()
4647 PreSL1660 = (RegValue == IUSC_PRE_SL1660); in usc_set_sdlc_mode()
4663 RegValue = 0x8e06; in usc_set_sdlc_mode()
4684 RegValue = 0x0001; /* Set Receive mode = external sync */ in usc_set_sdlc_mode()
4701 RegValue |= 0x0400; in usc_set_sdlc_mode()
4705 RegValue = 0x0606; in usc_set_sdlc_mode()
4708 RegValue |= BIT14; in usc_set_sdlc_mode()
4710 RegValue |= BIT15; in usc_set_sdlc_mode()
4712 RegValue |= BIT15 | BIT14; in usc_set_sdlc_mode()
4716 RegValue |= BIT13; in usc_set_sdlc_mode()
4721 RegValue |= BIT12; in usc_set_sdlc_mode()
4727 RegValue |= BIT4; in usc_set_sdlc_mode()
4730 usc_OutReg( info, CMR, RegValue ); in usc_set_sdlc_mode()
4731 info->cmr_value = RegValue; in usc_set_sdlc_mode()
4748 RegValue = 0x0500; in usc_set_sdlc_mode()
4751 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break; in usc_set_sdlc_mode()
4752 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break; in usc_set_sdlc_mode()
4753 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 | BIT13; break; in usc_set_sdlc_mode()
4754 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break; in usc_set_sdlc_mode()
4755 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 | BIT13; break; in usc_set_sdlc_mode()
4756 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14; break; in usc_set_sdlc_mode()
4757 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14 | BIT13; break; in usc_set_sdlc_mode()
4761 RegValue |= BIT9; in usc_set_sdlc_mode()
4763 RegValue |= ( BIT12 | BIT10 | BIT9 ); in usc_set_sdlc_mode()
4765 usc_OutReg( info, RMR, RegValue ); in usc_set_sdlc_mode()
4796 RegValue = usc_InReg( info, RICR ) & 0xc0; in usc_set_sdlc_mode()
4799 usc_OutReg( info, RICR, (u16)(0x030a | RegValue) ); in usc_set_sdlc_mode()
4801 usc_OutReg( info, RICR, (u16)(0x140a | RegValue) ); in usc_set_sdlc_mode()
4823 RegValue = 0x0400; in usc_set_sdlc_mode()
4826 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break; in usc_set_sdlc_mode()
4827 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break; in usc_set_sdlc_mode()
4828 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 | BIT13; break; in usc_set_sdlc_mode()
4829 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break; in usc_set_sdlc_mode()
4830 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 | BIT13; break; in usc_set_sdlc_mode()
4831 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14; break; in usc_set_sdlc_mode()
4832 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14 | BIT13; break; in usc_set_sdlc_mode()
4836 RegValue |= BIT9 | BIT8; in usc_set_sdlc_mode()
4838 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8); in usc_set_sdlc_mode()
4840 usc_OutReg( info, TMR, RegValue ); in usc_set_sdlc_mode()
4907 RegValue = 0x0f40; in usc_set_sdlc_mode()
4910 RegValue |= 0x0003; /* RxCLK from DPLL */ in usc_set_sdlc_mode()
4912 RegValue |= 0x0004; /* RxCLK from BRG0 */ in usc_set_sdlc_mode()
4914 RegValue |= 0x0006; /* RxCLK from TXC Input */ in usc_set_sdlc_mode()
4916 RegValue |= 0x0007; /* RxCLK from Port1 */ in usc_set_sdlc_mode()
4919 RegValue |= 0x0018; /* TxCLK from DPLL */ in usc_set_sdlc_mode()
4921 RegValue |= 0x0020; /* TxCLK from BRG0 */ in usc_set_sdlc_mode()
4923 RegValue |= 0x0038; /* RxCLK from TXC Input */ in usc_set_sdlc_mode()
4925 RegValue |= 0x0030; /* TxCLK from Port0 */ in usc_set_sdlc_mode()
4927 usc_OutReg( info, CMCR, RegValue ); in usc_set_sdlc_mode()
4945 RegValue = 0x0000; in usc_set_sdlc_mode()
4962 RegValue |= BIT10; in usc_set_sdlc_mode()
4966 RegValue |= BIT11; in usc_set_sdlc_mode()
4999 RegValue |= BIT4; /* enable BRG1 */ in usc_set_sdlc_mode()
5005 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break; in usc_set_sdlc_mode()
5007 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break; in usc_set_sdlc_mode()
5009 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 | BIT8; break; in usc_set_sdlc_mode()
5013 usc_OutReg( info, HCR, RegValue ); in usc_set_sdlc_mode()
5160 RegValue = 0x8080; in usc_set_sdlc_mode()
5163 case HDLC_PREAMBLE_LENGTH_16BITS: RegValue |= BIT10; break; in usc_set_sdlc_mode()
5164 case HDLC_PREAMBLE_LENGTH_32BITS: RegValue |= BIT11; break; in usc_set_sdlc_mode()
5165 case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 | BIT10; break; in usc_set_sdlc_mode()
5169 case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 | BIT12; break; in usc_set_sdlc_mode()
5170 case HDLC_PREAMBLE_PATTERN_ONES: RegValue |= BIT8; break; in usc_set_sdlc_mode()
5171 case HDLC_PREAMBLE_PATTERN_10: RegValue |= BIT9; break; in usc_set_sdlc_mode()
5172 case HDLC_PREAMBLE_PATTERN_01: RegValue |= BIT9 | BIT8; break; in usc_set_sdlc_mode()
5175 usc_OutReg( info, CCR, RegValue ); in usc_set_sdlc_mode()
5872 u16 RegValue; in usc_set_async_mode() local
5894 RegValue = 0; in usc_set_async_mode()
5896 RegValue |= BIT14; in usc_set_async_mode()
5897 usc_OutReg( info, CMR, RegValue ); in usc_set_async_mode()
5912 RegValue = 0; in usc_set_async_mode()
5915 RegValue |= BIT4 | BIT3 | BIT2; in usc_set_async_mode()
5918 RegValue |= BIT5; in usc_set_async_mode()
5920 RegValue |= BIT6; in usc_set_async_mode()
5923 usc_OutReg( info, RMR, RegValue ); in usc_set_async_mode()
5969 RegValue = 0; in usc_set_async_mode()
5972 RegValue |= BIT4 | BIT3 | BIT2; in usc_set_async_mode()
5975 RegValue |= BIT5; in usc_set_async_mode()
5977 RegValue |= BIT6; in usc_set_async_mode()
5980 usc_OutReg( info, TMR, RegValue ); in usc_set_async_mode()