Lines Matching defs:ucc_uart_pram

90 struct ucc_uart_pram {  struct
91 	struct ucc_slow_pram common;
92 	u8 res1[8];     	/* reserved */
93 	__be16 maxidl;  	/* Maximum idle chars */
94 	__be16 idlc;    	/* temp idle counter */
95 	__be16 brkcr;   	/* Break count register */
96 	__be16 parec;   	/* receive parity error counter */
97 	__be16 frmec;   	/* receive framing error counter */
98 	__be16 nosec;   	/* receive noise counter */
99 	__be16 brkec;   	/* receive break condition counter */
100 	__be16 brkln;   	/* last received break length */
101 	__be16 uaddr[2];	/* UART address character 1 & 2 */
102 	__be16 rtemp;   	/* Temp storage */
103 	__be16 toseq;   	/* Transmit out of sequence char */
104 	__be16 cchars[8];       /* control characters 1-8 */
105 	__be16 rccm;    	/* receive control character mask */
106 	__be16 rccr;    	/* receive control character register */
107 	__be16 rlbc;    	/* receive last break character */
108 	__be16 res2;    	/* reserved */
109 	__be32 res3;    	/* reserved, should be cleared */
110 	u8 res4;		/* reserved, should be cleared */
111 	u8 res5[3];     	/* reserved, should be cleared */
112 	__be32 res6;    	/* reserved, should be cleared */
113 	__be32 res7;    	/* reserved, should be cleared */
114 	__be32 res8;    	/* reserved, should be cleared */
115 	__be32 res9;    	/* reserved, should be cleared */
116 	__be32 res10;   	/* reserved, should be cleared */
117 	__be32 res11;   	/* reserved, should be cleared */
118 	__be32 res12;   	/* reserved, should be cleared */
119 	__be32 res13;   	/* reserved, should be cleared */
121 	__be16 supsmr;  	/* 0x90, Shadow UPSMR */
122 	__be16 res92;   	/* 0x92, reserved, initialize to 0 */
123 	__be32 rx_state;	/* 0x94, RX state, initialize to 0 */
124 	__be32 rx_cnt;  	/* 0x98, RX count, initialize to 0 */
125 	u8 rx_length;   	/* 0x9C, Char length, set to 1+CL+PEN+1+SL */
126 	u8 rx_bitmark;  	/* 0x9D, reserved, initialize to 0 */
127 	u8 rx_temp_dlst_qe;     /* 0x9E, reserved, initialize to 0 */
128 	u8 res14[0xBC - 0x9F];  /* reserved */
129 	__be32 dump_ptr;	/* 0xBC, Dump pointer */
130 	__be32 rx_frame_rem;    /* 0xC0, reserved, initialize to 0 */
131 	u8 rx_frame_rem_size;   /* 0xC4, reserved, initialize to 0 */
132 	u8 tx_mode;     	/* 0xC5, mode, 0=AHDLC, 1=UART */
133 	__be16 tx_state;	/* 0xC6, TX state */
134 	u8 res15[0xD0 - 0xC8];  /* reserved */
135 	__be32 resD0;   	/* 0xD0, reserved, initialize to 0 */
136 	u8 resD4;       	/* 0xD4, reserved, initialize to 0 */
137 	__be16 resD5;   	/* 0xD5, reserved, initialize to 0 */