Lines Matching refs:rd_regl
73 reg = rd_regl(port, ureg->sirfsoc_tx_fifo_status); in sirfsoc_uart_tx_empty()
84 if (!(rd_regl(port, ureg->sirfsoc_afc_ctrl) & in sirfsoc_uart_get_mctrl()
112 rd_regl(port, ureg->sirfsoc_line_ctrl) | in sirfsoc_uart_set_mctrl()
116 rd_regl(port, ureg->sirfsoc_mode1) | in sirfsoc_uart_set_mctrl()
121 rd_regl(port, ureg->sirfsoc_line_ctrl) & in sirfsoc_uart_set_mctrl()
125 rd_regl(port, ureg->sirfsoc_mode1) & in sirfsoc_uart_set_mctrl()
132 current_val = rd_regl(port, ureg->sirfsoc_afc_ctrl) & ~0xFF; in sirfsoc_uart_set_mctrl()
156 rd_regl(port, ureg->sirfsoc_int_en_reg) & in sirfsoc_uart_stop_tx()
164 wr_regl(port, ureg->sirfsoc_tx_rx_en, rd_regl(port, in sirfsoc_uart_stop_tx()
168 rd_regl(port, ureg->sirfsoc_int_en_reg) & in sirfsoc_uart_stop_tx()
199 rd_regl(port, ureg->sirfsoc_int_en_reg)& in sirfsoc_uart_tx_with_dma()
215 rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl)| in sirfsoc_uart_tx_with_dma()
226 rd_regl(port, ureg->sirfsoc_int_en_reg)| in sirfsoc_uart_tx_with_dma()
236 rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl)& in sirfsoc_uart_tx_with_dma()
271 wr_regl(port, ureg->sirfsoc_tx_rx_en, rd_regl(port, in sirfsoc_uart_start_tx()
278 rd_regl(port, ureg->sirfsoc_int_en_reg)| in sirfsoc_uart_start_tx()
296 rd_regl(port, ureg->sirfsoc_int_en_reg) & in sirfsoc_uart_stop_rx()
309 rd_regl(port, ureg->sirfsoc_int_en_reg)& in sirfsoc_uart_stop_rx()
330 rd_regl(port, ureg->sirfsoc_afc_ctrl) & ~0x3FF); in sirfsoc_uart_disable_ms()
333 rd_regl(port, ureg->sirfsoc_int_en_reg)& in sirfsoc_uart_disable_ms()
365 rd_regl(port, ureg->sirfsoc_afc_ctrl) | in sirfsoc_uart_enable_ms()
370 rd_regl(port, ureg->sirfsoc_int_en_reg) in sirfsoc_uart_enable_ms()
384 unsigned long ulcon = rd_regl(port, ureg->sirfsoc_line_ctrl); in sirfsoc_uart_break_ctl()
404 while (!(rd_regl(port, ureg->sirfsoc_rx_fifo_status) & in sirfsoc_uart_pio_rx_chars()
406 ch = rd_regl(port, ureg->sirfsoc_rx_fifo_data) | in sirfsoc_uart_pio_rx_chars()
430 !(rd_regl(port, ureg->sirfsoc_tx_fifo_status) & in sirfsoc_uart_pio_tx_chars()
479 intr_status = rd_regl(port, ureg->sirfsoc_int_st_reg); in sirfsoc_uart_isr()
481 intr_status &= rd_regl(port, ureg->sirfsoc_int_en_reg); in sirfsoc_uart_isr()
512 cts_status = rd_regl(port, ureg->sirfsoc_afc_ctrl) & in sirfsoc_uart_isr()
536 rd_regl(port, ureg->sirfsoc_int_en_reg) in sirfsoc_uart_isr()
539 rd_regl(port, ureg->sirfsoc_int_en_reg) in sirfsoc_uart_isr()
551 rd_regl(port, ureg->sirfsoc_int_en_reg) in sirfsoc_uart_isr()
554 rd_regl(port, ureg->sirfsoc_int_en_reg) in sirfsoc_uart_isr()
581 (rd_regl(port, ureg->sirfsoc_tx_fifo_status) & in sirfsoc_uart_isr()
603 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) & in sirfsoc_uart_start_next_rx_dma()
624 rd_regl(port, ureg->sirfsoc_int_en_reg) | in sirfsoc_uart_start_next_rx_dma()
825 txfifo_op_reg = rd_regl(port, ureg->sirfsoc_tx_fifo_op); in sirfsoc_uart_set_termios()
862 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) & in sirfsoc_uart_set_termios()
866 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) | in sirfsoc_uart_set_termios()
915 rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl) | in sirfsoc_uart_startup()
918 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) | in sirfsoc_uart_startup()
921 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) & in sirfsoc_uart_startup()
967 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) | in sirfsoc_uart_startup()
986 rd_regl(port, ureg->sirfsoc_int_en_reg) | in sirfsoc_uart_startup()
1026 while (((rd_regl(port, ureg->sirfsoc_rx_fifo_status) & in sirfsoc_uart_shutdown()
1121 while (rd_regl(port, ureg->sirfsoc_tx_fifo_status) & in sirfsoc_uart_console_putchar()
1217 ((rd_regl(port, ureg->sirfsoc_rx_fifo_status) & in sirfsoc_uart_rx_dma_hrtimer_callback()
1222 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) | in sirfsoc_uart_rx_dma_hrtimer_callback()
1237 while (!(rd_regl(port, ureg->sirfsoc_rx_fifo_status) & in sirfsoc_uart_rx_dma_hrtimer_callback()
1240 rd_regl(port, ureg->sirfsoc_rx_fifo_data); in sirfsoc_uart_rx_dma_hrtimer_callback()
1247 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) & in sirfsoc_uart_rx_dma_hrtimer_callback()