Lines Matching refs:tup
138 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup);
139 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup);
141 static inline unsigned long tegra_uart_read(struct tegra_uart_port *tup, in tegra_uart_read() argument
144 return readl(tup->uport.membase + (reg << tup->uport.regshift)); in tegra_uart_read()
147 static inline void tegra_uart_write(struct tegra_uart_port *tup, unsigned val, in tegra_uart_write() argument
150 writel(val, tup->uport.membase + (reg << tup->uport.regshift)); in tegra_uart_write()
160 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_get_mctrl() local
171 if (tup->enable_modem_interrupt) in tegra_uart_get_mctrl()
176 static void set_rts(struct tegra_uart_port *tup, bool active) in set_rts() argument
180 mcr = tup->mcr_shadow; in set_rts()
185 if (mcr != tup->mcr_shadow) { in set_rts()
186 tegra_uart_write(tup, mcr, UART_MCR); in set_rts()
187 tup->mcr_shadow = mcr; in set_rts()
191 static void set_dtr(struct tegra_uart_port *tup, bool active) in set_dtr() argument
195 mcr = tup->mcr_shadow; in set_dtr()
200 if (mcr != tup->mcr_shadow) { in set_dtr()
201 tegra_uart_write(tup, mcr, UART_MCR); in set_dtr()
202 tup->mcr_shadow = mcr; in set_dtr()
208 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_set_mctrl() local
212 mcr = tup->mcr_shadow; in tegra_uart_set_mctrl()
213 tup->rts_active = !!(mctrl & TIOCM_RTS); in tegra_uart_set_mctrl()
214 set_rts(tup, tup->rts_active); in tegra_uart_set_mctrl()
217 set_dtr(tup, dtr_enable); in tegra_uart_set_mctrl()
222 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_break_ctl() local
225 lcr = tup->lcr_shadow; in tegra_uart_break_ctl()
230 tegra_uart_write(tup, lcr, UART_LCR); in tegra_uart_break_ctl()
231 tup->lcr_shadow = lcr; in tegra_uart_break_ctl()
243 static void tegra_uart_wait_cycle_time(struct tegra_uart_port *tup, in tegra_uart_wait_cycle_time() argument
246 if (tup->current_baud) in tegra_uart_wait_cycle_time()
247 udelay(DIV_ROUND_UP(cycles * 1000000, tup->current_baud * 16)); in tegra_uart_wait_cycle_time()
251 static void tegra_uart_wait_sym_time(struct tegra_uart_port *tup, in tegra_uart_wait_sym_time() argument
254 if (tup->current_baud) in tegra_uart_wait_sym_time()
255 udelay(DIV_ROUND_UP(syms * tup->symb_bit * 1000000, in tegra_uart_wait_sym_time()
256 tup->current_baud)); in tegra_uart_wait_sym_time()
259 static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits) in tegra_uart_fifo_reset() argument
261 unsigned long fcr = tup->fcr_shadow; in tegra_uart_fifo_reset()
263 if (tup->cdata->allow_txfifo_reset_fifo_mode) { in tegra_uart_fifo_reset()
265 tegra_uart_write(tup, fcr, UART_FCR); in tegra_uart_fifo_reset()
268 tegra_uart_write(tup, fcr, UART_FCR); in tegra_uart_fifo_reset()
271 tegra_uart_write(tup, fcr, UART_FCR); in tegra_uart_fifo_reset()
273 tegra_uart_write(tup, fcr, UART_FCR); in tegra_uart_fifo_reset()
277 tegra_uart_read(tup, UART_SCR); in tegra_uart_fifo_reset()
284 tegra_uart_wait_cycle_time(tup, 32); in tegra_uart_fifo_reset()
287 static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud) in tegra_set_baudrate() argument
294 if (tup->current_baud == baud) in tegra_set_baudrate()
297 if (tup->cdata->support_clk_src_div) { in tegra_set_baudrate()
299 ret = clk_set_rate(tup->uart_clk, rate); in tegra_set_baudrate()
301 dev_err(tup->uport.dev, in tegra_set_baudrate()
307 rate = clk_get_rate(tup->uart_clk); in tegra_set_baudrate()
311 lcr = tup->lcr_shadow; in tegra_set_baudrate()
313 tegra_uart_write(tup, lcr, UART_LCR); in tegra_set_baudrate()
315 tegra_uart_write(tup, divisor & 0xFF, UART_TX); in tegra_set_baudrate()
316 tegra_uart_write(tup, ((divisor >> 8) & 0xFF), UART_IER); in tegra_set_baudrate()
319 tegra_uart_write(tup, lcr, UART_LCR); in tegra_set_baudrate()
322 tegra_uart_read(tup, UART_SCR); in tegra_set_baudrate()
324 tup->current_baud = baud; in tegra_set_baudrate()
327 tegra_uart_wait_sym_time(tup, 2); in tegra_set_baudrate()
331 static char tegra_uart_decode_rx_error(struct tegra_uart_port *tup, in tegra_uart_decode_rx_error() argument
340 tup->uport.icount.overrun++; in tegra_uart_decode_rx_error()
341 dev_err(tup->uport.dev, "Got overrun errors\n"); in tegra_uart_decode_rx_error()
345 tup->uport.icount.parity++; in tegra_uart_decode_rx_error()
346 dev_err(tup->uport.dev, "Got Parity errors\n"); in tegra_uart_decode_rx_error()
349 tup->uport.icount.frame++; in tegra_uart_decode_rx_error()
350 dev_err(tup->uport.dev, "Got frame errors\n"); in tegra_uart_decode_rx_error()
352 dev_err(tup->uport.dev, "Got Break\n"); in tegra_uart_decode_rx_error()
353 tup->uport.icount.brk++; in tegra_uart_decode_rx_error()
356 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_RCVR); in tegra_uart_decode_rx_error()
372 static void tegra_uart_fill_tx_fifo(struct tegra_uart_port *tup, int max_bytes) in tegra_uart_fill_tx_fifo() argument
374 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_fill_tx_fifo()
379 if (tup->cdata->tx_fifo_full_status) { in tegra_uart_fill_tx_fifo()
380 unsigned long lsr = tegra_uart_read(tup, UART_LSR); in tegra_uart_fill_tx_fifo()
384 tegra_uart_write(tup, xmit->buf[xmit->tail], UART_TX); in tegra_uart_fill_tx_fifo()
386 tup->uport.icount.tx++; in tegra_uart_fill_tx_fifo()
390 static void tegra_uart_start_pio_tx(struct tegra_uart_port *tup, in tegra_uart_start_pio_tx() argument
396 tup->tx_in_progress = TEGRA_UART_TX_PIO; in tegra_uart_start_pio_tx()
397 tup->tx_bytes = bytes; in tegra_uart_start_pio_tx()
398 tup->ier_shadow |= UART_IER_THRI; in tegra_uart_start_pio_tx()
399 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_start_pio_tx()
404 struct tegra_uart_port *tup = args; in tegra_uart_tx_dma_complete() local
405 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_tx_dma_complete()
410 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state); in tegra_uart_tx_dma_complete()
411 count = tup->tx_bytes_requested - state.residue; in tegra_uart_tx_dma_complete()
412 async_tx_ack(tup->tx_dma_desc); in tegra_uart_tx_dma_complete()
413 spin_lock_irqsave(&tup->uport.lock, flags); in tegra_uart_tx_dma_complete()
415 tup->tx_in_progress = 0; in tegra_uart_tx_dma_complete()
417 uart_write_wakeup(&tup->uport); in tegra_uart_tx_dma_complete()
418 tegra_uart_start_next_tx(tup); in tegra_uart_tx_dma_complete()
419 spin_unlock_irqrestore(&tup->uport.lock, flags); in tegra_uart_tx_dma_complete()
422 static int tegra_uart_start_tx_dma(struct tegra_uart_port *tup, in tegra_uart_start_tx_dma() argument
425 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_start_tx_dma()
428 dma_sync_single_for_device(tup->uport.dev, tup->tx_dma_buf_phys, in tegra_uart_start_tx_dma()
431 tup->tx_bytes = count & ~(0xF); in tegra_uart_start_tx_dma()
432 tx_phys_addr = tup->tx_dma_buf_phys + xmit->tail; in tegra_uart_start_tx_dma()
433 tup->tx_dma_desc = dmaengine_prep_slave_single(tup->tx_dma_chan, in tegra_uart_start_tx_dma()
434 tx_phys_addr, tup->tx_bytes, DMA_MEM_TO_DEV, in tegra_uart_start_tx_dma()
436 if (!tup->tx_dma_desc) { in tegra_uart_start_tx_dma()
437 dev_err(tup->uport.dev, "Not able to get desc for Tx\n"); in tegra_uart_start_tx_dma()
441 tup->tx_dma_desc->callback = tegra_uart_tx_dma_complete; in tegra_uart_start_tx_dma()
442 tup->tx_dma_desc->callback_param = tup; in tegra_uart_start_tx_dma()
443 tup->tx_in_progress = TEGRA_UART_TX_DMA; in tegra_uart_start_tx_dma()
444 tup->tx_bytes_requested = tup->tx_bytes; in tegra_uart_start_tx_dma()
445 tup->tx_cookie = dmaengine_submit(tup->tx_dma_desc); in tegra_uart_start_tx_dma()
446 dma_async_issue_pending(tup->tx_dma_chan); in tegra_uart_start_tx_dma()
450 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup) in tegra_uart_start_next_tx() argument
454 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_start_next_tx()
462 tegra_uart_start_pio_tx(tup, count); in tegra_uart_start_next_tx()
464 tegra_uart_start_pio_tx(tup, BYTES_TO_ALIGN(tail)); in tegra_uart_start_next_tx()
466 tegra_uart_start_tx_dma(tup, count); in tegra_uart_start_next_tx()
472 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_start_tx() local
475 if (!uart_circ_empty(xmit) && !tup->tx_in_progress) in tegra_uart_start_tx()
476 tegra_uart_start_next_tx(tup); in tegra_uart_start_tx()
481 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_tx_empty() local
486 if (!tup->tx_in_progress) { in tegra_uart_tx_empty()
487 unsigned long lsr = tegra_uart_read(tup, UART_LSR); in tegra_uart_tx_empty()
497 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_stop_tx() local
498 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_stop_tx()
502 if (tup->tx_in_progress != TEGRA_UART_TX_DMA) in tegra_uart_stop_tx()
505 dmaengine_terminate_all(tup->tx_dma_chan); in tegra_uart_stop_tx()
506 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state); in tegra_uart_stop_tx()
507 count = tup->tx_bytes_requested - state.residue; in tegra_uart_stop_tx()
508 async_tx_ack(tup->tx_dma_desc); in tegra_uart_stop_tx()
510 tup->tx_in_progress = 0; in tegra_uart_stop_tx()
513 static void tegra_uart_handle_tx_pio(struct tegra_uart_port *tup) in tegra_uart_handle_tx_pio() argument
515 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_handle_tx_pio()
517 tegra_uart_fill_tx_fifo(tup, tup->tx_bytes); in tegra_uart_handle_tx_pio()
518 tup->tx_in_progress = 0; in tegra_uart_handle_tx_pio()
520 uart_write_wakeup(&tup->uport); in tegra_uart_handle_tx_pio()
521 tegra_uart_start_next_tx(tup); in tegra_uart_handle_tx_pio()
524 static void tegra_uart_handle_rx_pio(struct tegra_uart_port *tup, in tegra_uart_handle_rx_pio() argument
532 lsr = tegra_uart_read(tup, UART_LSR); in tegra_uart_handle_rx_pio()
536 flag = tegra_uart_decode_rx_error(tup, lsr); in tegra_uart_handle_rx_pio()
537 ch = (unsigned char) tegra_uart_read(tup, UART_RX); in tegra_uart_handle_rx_pio()
538 tup->uport.icount.rx++; in tegra_uart_handle_rx_pio()
540 if (!uart_handle_sysrq_char(&tup->uport, ch) && tty) in tegra_uart_handle_rx_pio()
545 static void tegra_uart_copy_rx_to_tty(struct tegra_uart_port *tup, in tegra_uart_copy_rx_to_tty() argument
555 tup->uport.icount.rx += count; in tegra_uart_copy_rx_to_tty()
557 dev_err(tup->uport.dev, "No tty port\n"); in tegra_uart_copy_rx_to_tty()
560 dma_sync_single_for_cpu(tup->uport.dev, tup->rx_dma_buf_phys, in tegra_uart_copy_rx_to_tty()
563 ((unsigned char *)(tup->rx_dma_buf_virt)), count); in tegra_uart_copy_rx_to_tty()
566 dev_err(tup->uport.dev, "RxData copy to tty layer failed\n"); in tegra_uart_copy_rx_to_tty()
568 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys, in tegra_uart_copy_rx_to_tty()
572 static void tegra_uart_rx_buffer_push(struct tegra_uart_port *tup, in tegra_uart_rx_buffer_push() argument
575 struct tty_port *port = &tup->uport.state->port; in tegra_uart_rx_buffer_push()
579 async_tx_ack(tup->rx_dma_desc); in tegra_uart_rx_buffer_push()
580 count = tup->rx_bytes_requested - residue; in tegra_uart_rx_buffer_push()
583 tegra_uart_copy_rx_to_tty(tup, port, count); in tegra_uart_rx_buffer_push()
585 tegra_uart_handle_rx_pio(tup, port); in tegra_uart_rx_buffer_push()
594 struct tegra_uart_port *tup = args; in tegra_uart_rx_dma_complete() local
595 struct uart_port *u = &tup->uport; in tegra_uart_rx_dma_complete()
602 status = dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); in tegra_uart_rx_dma_complete()
605 dev_dbg(tup->uport.dev, "RX DMA is in progress\n"); in tegra_uart_rx_dma_complete()
610 if (tup->rts_active) in tegra_uart_rx_dma_complete()
611 set_rts(tup, false); in tegra_uart_rx_dma_complete()
613 tegra_uart_rx_buffer_push(tup, 0); in tegra_uart_rx_dma_complete()
614 tegra_uart_start_rx_dma(tup); in tegra_uart_rx_dma_complete()
617 if (tup->rts_active) in tegra_uart_rx_dma_complete()
618 set_rts(tup, true); in tegra_uart_rx_dma_complete()
624 static void tegra_uart_handle_rx_dma(struct tegra_uart_port *tup) in tegra_uart_handle_rx_dma() argument
629 if (tup->rts_active) in tegra_uart_handle_rx_dma()
630 set_rts(tup, false); in tegra_uart_handle_rx_dma()
632 dmaengine_terminate_all(tup->rx_dma_chan); in tegra_uart_handle_rx_dma()
633 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); in tegra_uart_handle_rx_dma()
634 tegra_uart_rx_buffer_push(tup, state.residue); in tegra_uart_handle_rx_dma()
635 tegra_uart_start_rx_dma(tup); in tegra_uart_handle_rx_dma()
637 if (tup->rts_active) in tegra_uart_handle_rx_dma()
638 set_rts(tup, true); in tegra_uart_handle_rx_dma()
641 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup) in tegra_uart_start_rx_dma() argument
645 tup->rx_dma_desc = dmaengine_prep_slave_single(tup->rx_dma_chan, in tegra_uart_start_rx_dma()
646 tup->rx_dma_buf_phys, count, DMA_DEV_TO_MEM, in tegra_uart_start_rx_dma()
648 if (!tup->rx_dma_desc) { in tegra_uart_start_rx_dma()
649 dev_err(tup->uport.dev, "Not able to get desc for Rx\n"); in tegra_uart_start_rx_dma()
653 tup->rx_dma_desc->callback = tegra_uart_rx_dma_complete; in tegra_uart_start_rx_dma()
654 tup->rx_dma_desc->callback_param = tup; in tegra_uart_start_rx_dma()
655 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys, in tegra_uart_start_rx_dma()
657 tup->rx_bytes_requested = count; in tegra_uart_start_rx_dma()
658 tup->rx_cookie = dmaengine_submit(tup->rx_dma_desc); in tegra_uart_start_rx_dma()
659 dma_async_issue_pending(tup->rx_dma_chan); in tegra_uart_start_rx_dma()
665 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_handle_modem_signal_change() local
668 msr = tegra_uart_read(tup, UART_MSR); in tegra_uart_handle_modem_signal_change()
673 tup->uport.icount.rng++; in tegra_uart_handle_modem_signal_change()
675 tup->uport.icount.dsr++; in tegra_uart_handle_modem_signal_change()
678 uart_handle_dcd_change(&tup->uport, msr & UART_MSR_DCD); in tegra_uart_handle_modem_signal_change()
681 uart_handle_cts_change(&tup->uport, msr & UART_MSR_CTS); in tegra_uart_handle_modem_signal_change()
686 struct tegra_uart_port *tup = data; in tegra_uart_isr() local
687 struct uart_port *u = &tup->uport; in tegra_uart_isr()
695 iir = tegra_uart_read(tup, UART_IIR); in tegra_uart_isr()
698 tegra_uart_handle_rx_dma(tup); in tegra_uart_isr()
699 if (tup->rx_in_progress) { in tegra_uart_isr()
700 ier = tup->ier_shadow; in tegra_uart_isr()
703 tup->ier_shadow = ier; in tegra_uart_isr()
704 tegra_uart_write(tup, ier, UART_IER); in tegra_uart_isr()
717 tup->ier_shadow &= ~UART_IER_THRI; in tegra_uart_isr()
718 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_isr()
719 tegra_uart_handle_tx_pio(tup); in tegra_uart_isr()
728 ier = tup->ier_shadow; in tegra_uart_isr()
730 tegra_uart_write(tup, ier, UART_IER); in tegra_uart_isr()
733 tup->ier_shadow = ier; in tegra_uart_isr()
734 tegra_uart_write(tup, ier, UART_IER); in tegra_uart_isr()
739 tegra_uart_decode_rx_error(tup, in tegra_uart_isr()
740 tegra_uart_read(tup, UART_LSR)); in tegra_uart_isr()
752 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_stop_rx() local
756 if (tup->rts_active) in tegra_uart_stop_rx()
757 set_rts(tup, false); in tegra_uart_stop_rx()
759 if (!tup->rx_in_progress) in tegra_uart_stop_rx()
762 tegra_uart_wait_sym_time(tup, 1); /* wait a character interval */ in tegra_uart_stop_rx()
764 ier = tup->ier_shadow; in tegra_uart_stop_rx()
767 tup->ier_shadow = ier; in tegra_uart_stop_rx()
768 tegra_uart_write(tup, ier, UART_IER); in tegra_uart_stop_rx()
769 tup->rx_in_progress = 0; in tegra_uart_stop_rx()
770 dmaengine_terminate_all(tup->rx_dma_chan); in tegra_uart_stop_rx()
771 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); in tegra_uart_stop_rx()
772 tegra_uart_rx_buffer_push(tup, state.residue); in tegra_uart_stop_rx()
775 static void tegra_uart_hw_deinit(struct tegra_uart_port *tup) in tegra_uart_hw_deinit() argument
778 unsigned long char_time = DIV_ROUND_UP(10000000, tup->current_baud); in tegra_uart_hw_deinit()
779 unsigned long fifo_empty_time = tup->uport.fifosize * char_time; in tegra_uart_hw_deinit()
786 tegra_uart_write(tup, 0, UART_IER); in tegra_uart_hw_deinit()
788 lsr = tegra_uart_read(tup, UART_LSR); in tegra_uart_hw_deinit()
790 msr = tegra_uart_read(tup, UART_MSR); in tegra_uart_hw_deinit()
791 mcr = tegra_uart_read(tup, UART_MCR); in tegra_uart_hw_deinit()
793 dev_err(tup->uport.dev, in tegra_uart_hw_deinit()
802 msr = tegra_uart_read(tup, UART_MSR); in tegra_uart_hw_deinit()
803 mcr = tegra_uart_read(tup, UART_MCR); in tegra_uart_hw_deinit()
806 dev_err(tup->uport.dev, in tegra_uart_hw_deinit()
810 lsr = tegra_uart_read(tup, UART_LSR); in tegra_uart_hw_deinit()
814 spin_lock_irqsave(&tup->uport.lock, flags); in tegra_uart_hw_deinit()
816 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR); in tegra_uart_hw_deinit()
817 tup->current_baud = 0; in tegra_uart_hw_deinit()
818 spin_unlock_irqrestore(&tup->uport.lock, flags); in tegra_uart_hw_deinit()
820 clk_disable_unprepare(tup->uart_clk); in tegra_uart_hw_deinit()
823 static int tegra_uart_hw_init(struct tegra_uart_port *tup) in tegra_uart_hw_init() argument
827 tup->fcr_shadow = 0; in tegra_uart_hw_init()
828 tup->mcr_shadow = 0; in tegra_uart_hw_init()
829 tup->lcr_shadow = 0; in tegra_uart_hw_init()
830 tup->ier_shadow = 0; in tegra_uart_hw_init()
831 tup->current_baud = 0; in tegra_uart_hw_init()
833 clk_prepare_enable(tup->uart_clk); in tegra_uart_hw_init()
836 reset_control_assert(tup->rst); in tegra_uart_hw_init()
838 reset_control_deassert(tup->rst); in tegra_uart_hw_init()
840 tup->rx_in_progress = 0; in tegra_uart_hw_init()
841 tup->tx_in_progress = 0; in tegra_uart_hw_init()
861 tup->fcr_shadow = UART_FCR_ENABLE_FIFO; in tegra_uart_hw_init()
862 tup->fcr_shadow |= UART_FCR_R_TRIG_01; in tegra_uart_hw_init()
863 tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B; in tegra_uart_hw_init()
864 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); in tegra_uart_hw_init()
867 tegra_uart_read(tup, UART_SCR); in tegra_uart_hw_init()
874 tegra_uart_wait_cycle_time(tup, 3); in tegra_uart_hw_init()
881 tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR; in tegra_uart_hw_init()
882 tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD); in tegra_uart_hw_init()
883 tup->fcr_shadow |= UART_FCR_DMA_SELECT; in tegra_uart_hw_init()
884 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); in tegra_uart_hw_init()
886 ret = tegra_uart_start_rx_dma(tup); in tegra_uart_hw_init()
888 dev_err(tup->uport.dev, "Not able to start Rx DMA\n"); in tegra_uart_hw_init()
891 tup->rx_in_progress = 1; in tegra_uart_hw_init()
911 tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE | TEGRA_UART_IER_EORD; in tegra_uart_hw_init()
912 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_hw_init()
916 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup, in tegra_uart_dma_channel_free() argument
920 dmaengine_terminate_all(tup->rx_dma_chan); in tegra_uart_dma_channel_free()
921 dma_release_channel(tup->rx_dma_chan); in tegra_uart_dma_channel_free()
922 dma_free_coherent(tup->uport.dev, TEGRA_UART_RX_DMA_BUFFER_SIZE, in tegra_uart_dma_channel_free()
923 tup->rx_dma_buf_virt, tup->rx_dma_buf_phys); in tegra_uart_dma_channel_free()
924 tup->rx_dma_chan = NULL; in tegra_uart_dma_channel_free()
925 tup->rx_dma_buf_phys = 0; in tegra_uart_dma_channel_free()
926 tup->rx_dma_buf_virt = NULL; in tegra_uart_dma_channel_free()
928 dmaengine_terminate_all(tup->tx_dma_chan); in tegra_uart_dma_channel_free()
929 dma_release_channel(tup->tx_dma_chan); in tegra_uart_dma_channel_free()
930 dma_unmap_single(tup->uport.dev, tup->tx_dma_buf_phys, in tegra_uart_dma_channel_free()
932 tup->tx_dma_chan = NULL; in tegra_uart_dma_channel_free()
933 tup->tx_dma_buf_phys = 0; in tegra_uart_dma_channel_free()
934 tup->tx_dma_buf_virt = NULL; in tegra_uart_dma_channel_free()
938 static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup, in tegra_uart_dma_channel_allocate() argument
947 dma_chan = dma_request_slave_channel_reason(tup->uport.dev, in tegra_uart_dma_channel_allocate()
951 dev_err(tup->uport.dev, in tegra_uart_dma_channel_allocate()
957 dma_buf = dma_alloc_coherent(tup->uport.dev, in tegra_uart_dma_channel_allocate()
961 dev_err(tup->uport.dev, in tegra_uart_dma_channel_allocate()
966 dma_sconfig.src_addr = tup->uport.mapbase; in tegra_uart_dma_channel_allocate()
969 tup->rx_dma_chan = dma_chan; in tegra_uart_dma_channel_allocate()
970 tup->rx_dma_buf_virt = dma_buf; in tegra_uart_dma_channel_allocate()
971 tup->rx_dma_buf_phys = dma_phys; in tegra_uart_dma_channel_allocate()
973 dma_phys = dma_map_single(tup->uport.dev, in tegra_uart_dma_channel_allocate()
974 tup->uport.state->xmit.buf, UART_XMIT_SIZE, in tegra_uart_dma_channel_allocate()
976 if (dma_mapping_error(tup->uport.dev, dma_phys)) { in tegra_uart_dma_channel_allocate()
977 dev_err(tup->uport.dev, "dma_map_single tx failed\n"); in tegra_uart_dma_channel_allocate()
981 dma_buf = tup->uport.state->xmit.buf; in tegra_uart_dma_channel_allocate()
982 dma_sconfig.dst_addr = tup->uport.mapbase; in tegra_uart_dma_channel_allocate()
985 tup->tx_dma_chan = dma_chan; in tegra_uart_dma_channel_allocate()
986 tup->tx_dma_buf_virt = dma_buf; in tegra_uart_dma_channel_allocate()
987 tup->tx_dma_buf_phys = dma_phys; in tegra_uart_dma_channel_allocate()
992 dev_err(tup->uport.dev, in tegra_uart_dma_channel_allocate()
994 tegra_uart_dma_channel_free(tup, dma_to_memory); in tegra_uart_dma_channel_allocate()
1003 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_startup() local
1006 ret = tegra_uart_dma_channel_allocate(tup, false); in tegra_uart_startup()
1012 ret = tegra_uart_dma_channel_allocate(tup, true); in tegra_uart_startup()
1018 ret = tegra_uart_hw_init(tup); in tegra_uart_startup()
1025 dev_name(u->dev), tup); in tegra_uart_startup()
1033 tegra_uart_dma_channel_free(tup, true); in tegra_uart_startup()
1035 tegra_uart_dma_channel_free(tup, false); in tegra_uart_startup()
1045 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_flush_buffer() local
1047 tup->tx_bytes = 0; in tegra_uart_flush_buffer()
1048 if (tup->tx_dma_chan) in tegra_uart_flush_buffer()
1049 dmaengine_terminate_all(tup->tx_dma_chan); in tegra_uart_flush_buffer()
1054 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_shutdown() local
1056 tegra_uart_hw_deinit(tup); in tegra_uart_shutdown()
1058 tup->rx_in_progress = 0; in tegra_uart_shutdown()
1059 tup->tx_in_progress = 0; in tegra_uart_shutdown()
1061 tegra_uart_dma_channel_free(tup, true); in tegra_uart_shutdown()
1062 tegra_uart_dma_channel_free(tup, false); in tegra_uart_shutdown()
1063 free_irq(u->irq, tup); in tegra_uart_shutdown()
1068 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_enable_ms() local
1070 if (tup->enable_modem_interrupt) { in tegra_uart_enable_ms()
1071 tup->ier_shadow |= UART_IER_MSI; in tegra_uart_enable_ms()
1072 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_enable_ms()
1079 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_set_termios() local
1084 struct clk *parent_clk = clk_get_parent(tup->uart_clk); in tegra_uart_set_termios()
1086 int max_divider = (tup->cdata->support_clk_src_div) ? 0x7FFF : 0xFFFF; in tegra_uart_set_termios()
1092 if (tup->rts_active) in tegra_uart_set_termios()
1093 set_rts(tup, false); in tegra_uart_set_termios()
1096 tegra_uart_write(tup, tup->ier_shadow | UART_IER_RDI, UART_IER); in tegra_uart_set_termios()
1097 tegra_uart_read(tup, UART_IER); in tegra_uart_set_termios()
1098 tegra_uart_write(tup, 0, UART_IER); in tegra_uart_set_termios()
1099 tegra_uart_read(tup, UART_IER); in tegra_uart_set_termios()
1102 lcr = tup->lcr_shadow; in tegra_uart_set_termios()
1150 tegra_uart_write(tup, lcr, UART_LCR); in tegra_uart_set_termios()
1151 tup->lcr_shadow = lcr; in tegra_uart_set_termios()
1152 tup->symb_bit = symb_bit; in tegra_uart_set_termios()
1159 tegra_set_baudrate(tup, baud); in tegra_uart_set_termios()
1166 tup->mcr_shadow |= TEGRA_UART_MCR_CTS_EN; in tegra_uart_set_termios()
1167 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN; in tegra_uart_set_termios()
1168 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR); in tegra_uart_set_termios()
1170 if (tup->rts_active) in tegra_uart_set_termios()
1171 set_rts(tup, true); in tegra_uart_set_termios()
1173 tup->mcr_shadow &= ~TEGRA_UART_MCR_CTS_EN; in tegra_uart_set_termios()
1174 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN; in tegra_uart_set_termios()
1175 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR); in tegra_uart_set_termios()
1182 tegra_uart_read(tup, UART_IER); in tegra_uart_set_termios()
1185 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_set_termios()
1186 tegra_uart_read(tup, UART_IER); in tegra_uart_set_termios()
1223 struct tegra_uart_port *tup) in tegra_uart_parse_dt() argument
1233 tup->uport.line = port; in tegra_uart_parse_dt()
1235 tup->enable_modem_interrupt = of_property_read_bool(np, in tegra_uart_parse_dt()
1266 struct tegra_uart_port *tup; in tegra_uart_probe() local
1280 tup = devm_kzalloc(&pdev->dev, sizeof(*tup), GFP_KERNEL); in tegra_uart_probe()
1281 if (!tup) { in tegra_uart_probe()
1286 ret = tegra_uart_parse_dt(pdev, tup); in tegra_uart_probe()
1290 u = &tup->uport; in tegra_uart_probe()
1295 tup->cdata = cdata; in tegra_uart_probe()
1297 platform_set_drvdata(pdev, tup); in tegra_uart_probe()
1309 tup->uart_clk = devm_clk_get(&pdev->dev, NULL); in tegra_uart_probe()
1310 if (IS_ERR(tup->uart_clk)) { in tegra_uart_probe()
1312 return PTR_ERR(tup->uart_clk); in tegra_uart_probe()
1315 tup->rst = devm_reset_control_get(&pdev->dev, "serial"); in tegra_uart_probe()
1316 if (IS_ERR(tup->rst)) { in tegra_uart_probe()
1318 return PTR_ERR(tup->rst); in tegra_uart_probe()
1334 struct tegra_uart_port *tup = platform_get_drvdata(pdev); in tegra_uart_remove() local
1335 struct uart_port *u = &tup->uport; in tegra_uart_remove()
1344 struct tegra_uart_port *tup = dev_get_drvdata(dev); in tegra_uart_suspend() local
1345 struct uart_port *u = &tup->uport; in tegra_uart_suspend()
1352 struct tegra_uart_port *tup = dev_get_drvdata(dev); in tegra_uart_resume() local
1353 struct uart_port *u = &tup->uport; in tegra_uart_resume()