Lines Matching refs:priv
323 struct eg20t_port *priv = file->private_data; in port_show_regs() local
334 "PCH EG20T port[%d] regs:\n", priv->port.line); in port_show_regs()
339 "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER)); in port_show_regs()
341 "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR)); in port_show_regs()
343 "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR)); in port_show_regs()
345 "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR)); in port_show_regs()
347 "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR)); in port_show_regs()
349 "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR)); in port_show_regs()
352 ioread8(priv->membase + PCH_UART_BRCSR)); in port_show_regs()
354 lcr = ioread8(priv->membase + UART_LCR); in port_show_regs()
355 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); in port_show_regs()
357 "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL)); in port_show_regs()
359 "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM)); in port_show_regs()
360 iowrite8(lcr, priv->membase + UART_LCR); in port_show_regs()
438 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv, in pch_uart_hal_enable_interrupt() argument
441 u8 ier = ioread8(priv->membase + UART_IER); in pch_uart_hal_enable_interrupt()
443 iowrite8(ier, priv->membase + UART_IER); in pch_uart_hal_enable_interrupt()
446 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv, in pch_uart_hal_disable_interrupt() argument
449 u8 ier = ioread8(priv->membase + UART_IER); in pch_uart_hal_disable_interrupt()
451 iowrite8(ier, priv->membase + UART_IER); in pch_uart_hal_disable_interrupt()
454 static int pch_uart_hal_set_line(struct eg20t_port *priv, unsigned int baud, in pch_uart_hal_set_line() argument
461 div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud); in pch_uart_hal_set_line()
463 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div); in pch_uart_hal_set_line()
471 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity); in pch_uart_hal_set_line()
476 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits); in pch_uart_hal_set_line()
481 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb); in pch_uart_hal_set_line()
489 dev_dbg(priv->port.dev, "%s:baud = %u, div = %04x, lcr = %02x (%lu)\n", in pch_uart_hal_set_line()
491 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); in pch_uart_hal_set_line()
492 iowrite8(dll, priv->membase + PCH_UART_DLL); in pch_uart_hal_set_line()
493 iowrite8(dlm, priv->membase + PCH_UART_DLM); in pch_uart_hal_set_line()
494 iowrite8(lcr, priv->membase + UART_LCR); in pch_uart_hal_set_line()
499 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv, in pch_uart_hal_fifo_reset() argument
503 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n", in pch_uart_hal_fifo_reset()
508 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR); in pch_uart_hal_fifo_reset()
509 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag, in pch_uart_hal_fifo_reset()
510 priv->membase + UART_FCR); in pch_uart_hal_fifo_reset()
511 iowrite8(priv->fcr, priv->membase + UART_FCR); in pch_uart_hal_fifo_reset()
516 static int pch_uart_hal_set_fifo(struct eg20t_port *priv, in pch_uart_hal_set_fifo() argument
523 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n", in pch_uart_hal_set_fifo()
529 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n", in pch_uart_hal_set_fifo()
535 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n", in pch_uart_hal_set_fifo()
540 switch (priv->fifo_size) { in pch_uart_hal_set_fifo()
542 priv->trigger_level = in pch_uart_hal_set_fifo()
546 priv->trigger_level = in pch_uart_hal_set_fifo()
550 priv->trigger_level = in pch_uart_hal_set_fifo()
554 priv->trigger_level = in pch_uart_hal_set_fifo()
560 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR); in pch_uart_hal_set_fifo()
562 priv->membase + UART_FCR); in pch_uart_hal_set_fifo()
563 iowrite8(fcr, priv->membase + UART_FCR); in pch_uart_hal_set_fifo()
564 priv->fcr = fcr; in pch_uart_hal_set_fifo()
569 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv) in pch_uart_hal_get_modem() argument
571 unsigned int msr = ioread8(priv->membase + UART_MSR); in pch_uart_hal_get_modem()
572 priv->dmsr = msr & PCH_UART_MSR_DELTA; in pch_uart_hal_get_modem()
576 static void pch_uart_hal_write(struct eg20t_port *priv, in pch_uart_hal_write() argument
584 iowrite8(thr, priv->membase + PCH_UART_THR); in pch_uart_hal_write()
588 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf, in pch_uart_hal_read() argument
593 struct uart_port *port = &priv->port; in pch_uart_hal_read()
595 lsr = ioread8(priv->membase + UART_LSR); in pch_uart_hal_read()
596 for (i = 0, lsr = ioread8(priv->membase + UART_LSR); in pch_uart_hal_read()
598 lsr = ioread8(priv->membase + UART_LSR)) { in pch_uart_hal_read()
599 rbr = ioread8(priv->membase + PCH_UART_RBR); in pch_uart_hal_read()
618 static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv) in pch_uart_hal_get_iid() argument
620 return ioread8(priv->membase + UART_IIR) &\ in pch_uart_hal_get_iid()
624 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv) in pch_uart_hal_get_line_status() argument
626 return ioread8(priv->membase + UART_LSR); in pch_uart_hal_get_line_status()
629 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on) in pch_uart_hal_set_break() argument
633 lcr = ioread8(priv->membase + UART_LCR); in pch_uart_hal_set_break()
639 iowrite8(lcr, priv->membase + UART_LCR); in pch_uart_hal_set_break()
642 static int push_rx(struct eg20t_port *priv, const unsigned char *buf, in push_rx() argument
645 struct uart_port *port = &priv->port; in push_rx()
654 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf) in pop_tx_x() argument
657 struct uart_port *port = &priv->port; in pop_tx_x()
660 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n", in pop_tx_x()
670 static int dma_push_rx(struct eg20t_port *priv, int size) in dma_push_rx() argument
673 struct uart_port *port = &priv->port; in dma_push_rx()
684 tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size); in dma_push_rx()
693 struct eg20t_port *priv; in pch_free_dma() local
694 priv = container_of(port, struct eg20t_port, port); in pch_free_dma()
696 if (priv->chan_tx) { in pch_free_dma()
697 dma_release_channel(priv->chan_tx); in pch_free_dma()
698 priv->chan_tx = NULL; in pch_free_dma()
700 if (priv->chan_rx) { in pch_free_dma()
701 dma_release_channel(priv->chan_rx); in pch_free_dma()
702 priv->chan_rx = NULL; in pch_free_dma()
705 if (priv->rx_buf_dma) { in pch_free_dma()
706 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt, in pch_free_dma()
707 priv->rx_buf_dma); in pch_free_dma()
708 priv->rx_buf_virt = NULL; in pch_free_dma()
709 priv->rx_buf_dma = 0; in pch_free_dma()
734 struct eg20t_port *priv = in pch_request_dma() local
740 dma_dev = pci_get_slot(priv->pdev->bus, in pch_request_dma()
741 PCI_DEVFN(PCI_SLOT(priv->pdev->devfn), 0)); in pch_request_dma()
744 param = &priv->param_tx; in pch_request_dma()
746 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */ in pch_request_dma()
751 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n", in pch_request_dma()
755 priv->chan_tx = chan; in pch_request_dma()
758 param = &priv->param_rx; in pch_request_dma()
760 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */ in pch_request_dma()
765 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n", in pch_request_dma()
767 dma_release_channel(priv->chan_tx); in pch_request_dma()
768 priv->chan_tx = NULL; in pch_request_dma()
773 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize, in pch_request_dma()
774 &priv->rx_buf_dma, GFP_KERNEL); in pch_request_dma()
775 priv->chan_rx = chan; in pch_request_dma()
780 struct eg20t_port *priv = arg; in pch_dma_rx_complete() local
781 struct uart_port *port = &priv->port; in pch_dma_rx_complete()
784 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE); in pch_dma_rx_complete()
785 count = dma_push_rx(priv, priv->trigger_level); in pch_dma_rx_complete()
788 async_tx_ack(priv->desc_rx); in pch_dma_rx_complete()
789 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT | in pch_dma_rx_complete()
795 struct eg20t_port *priv = arg; in pch_dma_tx_complete() local
796 struct uart_port *port = &priv->port; in pch_dma_tx_complete()
798 struct scatterlist *sg = priv->sg_tx_p; in pch_dma_tx_complete()
801 for (i = 0; i < priv->nent; i++, sg++) { in pch_dma_tx_complete()
806 async_tx_ack(priv->desc_tx); in pch_dma_tx_complete()
807 dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE); in pch_dma_tx_complete()
808 priv->tx_dma_use = 0; in pch_dma_tx_complete()
809 priv->nent = 0; in pch_dma_tx_complete()
810 kfree(priv->sg_tx_p); in pch_dma_tx_complete()
811 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); in pch_dma_tx_complete()
814 static int pop_tx(struct eg20t_port *priv, int size) in pop_tx() argument
817 struct uart_port *port = &priv->port; in pop_tx()
827 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz); in pop_tx()
833 dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n", in pop_tx()
839 static int handle_rx_to(struct eg20t_port *priv) in handle_rx_to() argument
844 if (!priv->start_rx) { in handle_rx_to()
845 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT | in handle_rx_to()
849 buf = &priv->rxbuf; in handle_rx_to()
851 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size); in handle_rx_to()
852 ret = push_rx(priv, buf->buf, rx_size); in handle_rx_to()
860 static int handle_rx(struct eg20t_port *priv) in handle_rx() argument
862 return handle_rx_to(priv); in handle_rx()
865 static int dma_handle_rx(struct eg20t_port *priv) in dma_handle_rx() argument
867 struct uart_port *port = &priv->port; in dma_handle_rx()
871 priv = container_of(port, struct eg20t_port, port); in dma_handle_rx()
872 sg = &priv->sg_rx; in dma_handle_rx()
874 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */ in dma_handle_rx()
876 sg_dma_len(sg) = priv->trigger_level; in dma_handle_rx()
878 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt), in dma_handle_rx()
879 sg_dma_len(sg), (unsigned long)priv->rx_buf_virt & in dma_handle_rx()
882 sg_dma_address(sg) = priv->rx_buf_dma; in dma_handle_rx()
884 desc = dmaengine_prep_slave_sg(priv->chan_rx, in dma_handle_rx()
891 priv->desc_rx = desc; in dma_handle_rx()
893 desc->callback_param = priv; in dma_handle_rx()
895 dma_async_issue_pending(priv->chan_rx); in dma_handle_rx()
900 static unsigned int handle_tx(struct eg20t_port *priv) in handle_tx() argument
902 struct uart_port *port = &priv->port; in handle_tx()
909 if (!priv->start_tx) { in handle_tx()
910 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", in handle_tx()
912 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); in handle_tx()
913 priv->tx_empty = 1; in handle_tx()
917 fifo_size = max(priv->fifo_size, 1); in handle_tx()
919 if (pop_tx_x(priv, xmit->buf)) { in handle_tx()
920 pch_uart_hal_write(priv, xmit->buf, 1); in handle_tx()
929 tx_size = pop_tx(priv, size); in handle_tx()
935 priv->tx_empty = tx_empty; in handle_tx()
938 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); in handle_tx()
945 static unsigned int dma_handle_tx(struct eg20t_port *priv) in dma_handle_tx() argument
947 struct uart_port *port = &priv->port; in dma_handle_tx()
960 if (!priv->start_tx) { in dma_handle_tx()
961 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", in dma_handle_tx()
963 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); in dma_handle_tx()
964 priv->tx_empty = 1; in dma_handle_tx()
968 if (priv->tx_dma_use) { in dma_handle_tx()
969 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n", in dma_handle_tx()
971 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); in dma_handle_tx()
972 priv->tx_empty = 1; in dma_handle_tx()
976 fifo_size = max(priv->fifo_size, 1); in dma_handle_tx()
978 if (pop_tx_x(priv, xmit->buf)) { in dma_handle_tx()
979 pch_uart_hal_write(priv, xmit->buf, 1); in dma_handle_tx()
989 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__); in dma_handle_tx()
990 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); in dma_handle_tx()
1005 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n", in dma_handle_tx()
1008 priv->tx_dma_use = 1; in dma_handle_tx()
1010 priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC); in dma_handle_tx()
1011 if (!priv->sg_tx_p) { in dma_handle_tx()
1012 dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__); in dma_handle_tx()
1016 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */ in dma_handle_tx()
1017 sg = priv->sg_tx_p; in dma_handle_tx()
1028 sg = priv->sg_tx_p; in dma_handle_tx()
1031 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__); in dma_handle_tx()
1034 priv->nent = nent; in dma_handle_tx()
1047 desc = dmaengine_prep_slave_sg(priv->chan_tx, in dma_handle_tx()
1048 priv->sg_tx_p, nent, DMA_MEM_TO_DEV, in dma_handle_tx()
1051 dev_err(priv->port.dev, "%s:dmaengine_prep_slave_sg Failed\n", in dma_handle_tx()
1055 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE); in dma_handle_tx()
1056 priv->desc_tx = desc; in dma_handle_tx()
1058 desc->callback_param = priv; in dma_handle_tx()
1062 dma_async_issue_pending(priv->chan_tx); in dma_handle_tx()
1067 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr) in pch_uart_err_ir() argument
1069 struct uart_port *port = &priv->port; in pch_uart_err_ir()
1094 dev_err(&priv->pdev->dev, error_msg[i]); in pch_uart_err_ir()
1102 struct eg20t_port *priv = dev_id; in pch_uart_interrupt() local
1111 spin_lock_irqsave(&priv->lock, flags); in pch_uart_interrupt()
1114 iid = pch_uart_hal_get_iid(priv); in pch_uart_interrupt()
1119 lsr = pch_uart_hal_get_line_status(priv); in pch_uart_interrupt()
1122 pch_uart_err_ir(priv, lsr); in pch_uart_interrupt()
1129 if (priv->use_dma) { in pch_uart_interrupt()
1130 pch_uart_hal_disable_interrupt(priv, in pch_uart_interrupt()
1133 ret = dma_handle_rx(priv); in pch_uart_interrupt()
1135 pch_uart_hal_enable_interrupt(priv, in pch_uart_interrupt()
1139 ret = handle_rx(priv); in pch_uart_interrupt()
1144 ret = handle_rx_to(priv); in pch_uart_interrupt()
1148 if (priv->use_dma) in pch_uart_interrupt()
1149 ret = dma_handle_tx(priv); in pch_uart_interrupt()
1151 ret = handle_tx(priv); in pch_uart_interrupt()
1154 msr = pch_uart_hal_get_modem(priv); in pch_uart_interrupt()
1162 dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__, in pch_uart_interrupt()
1171 spin_unlock_irqrestore(&priv->lock, flags); in pch_uart_interrupt()
1179 struct eg20t_port *priv; in pch_uart_tx_empty() local
1181 priv = container_of(port, struct eg20t_port, port); in pch_uart_tx_empty()
1182 if (priv->tx_empty) in pch_uart_tx_empty()
1191 struct eg20t_port *priv; in pch_uart_get_mctrl() local
1195 priv = container_of(port, struct eg20t_port, port); in pch_uart_get_mctrl()
1196 modem = pch_uart_hal_get_modem(priv); in pch_uart_get_mctrl()
1216 struct eg20t_port *priv = container_of(port, struct eg20t_port, port); in pch_uart_set_mctrl() local
1225 if (priv->mcr & UART_MCR_AFE) in pch_uart_set_mctrl()
1229 iowrite8(mcr, priv->membase + UART_MCR); in pch_uart_set_mctrl()
1234 struct eg20t_port *priv; in pch_uart_stop_tx() local
1235 priv = container_of(port, struct eg20t_port, port); in pch_uart_stop_tx()
1236 priv->start_tx = 0; in pch_uart_stop_tx()
1237 priv->tx_dma_use = 0; in pch_uart_stop_tx()
1242 struct eg20t_port *priv; in pch_uart_start_tx() local
1244 priv = container_of(port, struct eg20t_port, port); in pch_uart_start_tx()
1246 if (priv->use_dma) { in pch_uart_start_tx()
1247 if (priv->tx_dma_use) { in pch_uart_start_tx()
1248 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n", in pch_uart_start_tx()
1254 priv->start_tx = 1; in pch_uart_start_tx()
1255 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); in pch_uart_start_tx()
1260 struct eg20t_port *priv; in pch_uart_stop_rx() local
1261 priv = container_of(port, struct eg20t_port, port); in pch_uart_stop_rx()
1262 priv->start_rx = 0; in pch_uart_stop_rx()
1263 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT | in pch_uart_stop_rx()
1270 struct eg20t_port *priv; in pch_uart_enable_ms() local
1271 priv = container_of(port, struct eg20t_port, port); in pch_uart_enable_ms()
1272 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT); in pch_uart_enable_ms()
1278 struct eg20t_port *priv; in pch_uart_break_ctl() local
1281 priv = container_of(port, struct eg20t_port, port); in pch_uart_break_ctl()
1282 spin_lock_irqsave(&priv->lock, flags); in pch_uart_break_ctl()
1283 pch_uart_hal_set_break(priv, ctl); in pch_uart_break_ctl()
1284 spin_unlock_irqrestore(&priv->lock, flags); in pch_uart_break_ctl()
1290 struct eg20t_port *priv; in pch_uart_startup() local
1295 priv = container_of(port, struct eg20t_port, port); in pch_uart_startup()
1296 priv->tx_empty = 1; in pch_uart_startup()
1299 priv->uartclk = port->uartclk; in pch_uart_startup()
1301 port->uartclk = priv->uartclk; in pch_uart_startup()
1303 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); in pch_uart_startup()
1304 ret = pch_uart_hal_set_line(priv, default_baud, in pch_uart_startup()
1310 switch (priv->fifo_size) { in pch_uart_startup()
1326 switch (priv->trigger) { in pch_uart_startup()
1331 trigger_level = priv->fifo_size / 4; in pch_uart_startup()
1334 trigger_level = priv->fifo_size / 2; in pch_uart_startup()
1338 trigger_level = priv->fifo_size - (priv->fifo_size / 8); in pch_uart_startup()
1342 priv->trigger_level = trigger_level; in pch_uart_startup()
1343 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, in pch_uart_startup()
1344 fifo_size, priv->trigger); in pch_uart_startup()
1348 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED, in pch_uart_startup()
1349 priv->irq_name, priv); in pch_uart_startup()
1353 if (priv->use_dma) in pch_uart_startup()
1356 priv->start_rx = 1; in pch_uart_startup()
1357 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT | in pch_uart_startup()
1366 struct eg20t_port *priv; in pch_uart_shutdown() local
1369 priv = container_of(port, struct eg20t_port, port); in pch_uart_shutdown()
1370 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); in pch_uart_shutdown()
1371 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO); in pch_uart_shutdown()
1372 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, in pch_uart_shutdown()
1375 dev_err(priv->port.dev, in pch_uart_shutdown()
1380 free_irq(priv->port.irq, priv); in pch_uart_shutdown()
1391 struct eg20t_port *priv; in pch_uart_set_termios() local
1394 priv = container_of(port, struct eg20t_port, port); in pch_uart_set_termios()
1424 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256)) in pch_uart_set_termios()
1425 priv->mcr |= UART_MCR_AFE; in pch_uart_set_termios()
1427 priv->mcr &= ~UART_MCR_AFE; in pch_uart_set_termios()
1433 spin_lock_irqsave(&priv->lock, flags); in pch_uart_set_termios()
1437 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb); in pch_uart_set_termios()
1441 pch_uart_set_mctrl(&priv->port, priv->port.mctrl); in pch_uart_set_termios()
1448 spin_unlock_irqrestore(&priv->lock, flags); in pch_uart_set_termios()
1458 struct eg20t_port *priv; in pch_uart_release_port() local
1460 priv = container_of(port, struct eg20t_port, port); in pch_uart_release_port()
1461 pci_iounmap(priv->pdev, priv->membase); in pch_uart_release_port()
1462 pci_release_regions(priv->pdev); in pch_uart_release_port()
1467 struct eg20t_port *priv; in pch_uart_request_port() local
1471 priv = container_of(port, struct eg20t_port, port); in pch_uart_request_port()
1472 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME); in pch_uart_request_port()
1476 membase = pci_iomap(priv->pdev, 1, 0); in pch_uart_request_port()
1478 pci_release_regions(priv->pdev); in pch_uart_request_port()
1481 priv->membase = port->membase = membase; in pch_uart_request_port()
1488 struct eg20t_port *priv; in pch_uart_config_port() local
1490 priv = container_of(port, struct eg20t_port, port); in pch_uart_config_port()
1492 port->type = priv->port_type; in pch_uart_config_port()
1500 struct eg20t_port *priv; in pch_uart_verify_port() local
1502 priv = container_of(port, struct eg20t_port, port); in pch_uart_verify_port()
1504 dev_info(priv->port.dev, in pch_uart_verify_port()
1506 priv->use_dma = 0; in pch_uart_verify_port()
1510 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n", in pch_uart_verify_port()
1514 if (!priv->use_dma) { in pch_uart_verify_port()
1516 if (priv->chan_rx) in pch_uart_verify_port()
1517 priv->use_dma = 1; in pch_uart_verify_port()
1519 dev_info(priv->port.dev, "PCH UART: %s\n", in pch_uart_verify_port()
1520 priv->use_dma ? in pch_uart_verify_port()
1567 struct eg20t_port *priv = in pch_uart_get_poll_char() local
1569 u8 lsr = ioread8(priv->membase + UART_LSR); in pch_uart_get_poll_char()
1574 return ioread8(priv->membase + PCH_UART_RBR); in pch_uart_get_poll_char()
1582 struct eg20t_port *priv = in pch_uart_put_poll_char() local
1588 ier = ioread8(priv->membase + UART_IER); in pch_uart_put_poll_char()
1589 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); in pch_uart_put_poll_char()
1591 wait_for_xmitr(priv, UART_LSR_THRE); in pch_uart_put_poll_char()
1595 iowrite8(c, priv->membase + PCH_UART_THR); in pch_uart_put_poll_char()
1601 wait_for_xmitr(priv, BOTH_EMPTY); in pch_uart_put_poll_char()
1602 iowrite8(ier, priv->membase + UART_IER); in pch_uart_put_poll_char()
1634 struct eg20t_port *priv = in pch_console_putchar() local
1637 wait_for_xmitr(priv, UART_LSR_THRE); in pch_console_putchar()
1638 iowrite8(ch, priv->membase + PCH_UART_THR); in pch_console_putchar()
1650 struct eg20t_port *priv; in pch_console_write() local
1656 priv = pch_uart_ports[co->index]; in pch_console_write()
1661 if (priv->port.sysrq) { in pch_console_write()
1667 priv_locked = spin_trylock(&priv->lock); in pch_console_write()
1668 port_locked = spin_trylock(&priv->port.lock); in pch_console_write()
1670 spin_lock(&priv->lock); in pch_console_write()
1671 spin_lock(&priv->port.lock); in pch_console_write()
1677 ier = ioread8(priv->membase + UART_IER); in pch_console_write()
1679 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); in pch_console_write()
1681 uart_console_write(&priv->port, s, count, pch_console_putchar); in pch_console_write()
1687 wait_for_xmitr(priv, BOTH_EMPTY); in pch_console_write()
1688 iowrite8(ier, priv->membase + UART_IER); in pch_console_write()
1691 spin_unlock(&priv->port.lock); in pch_console_write()
1693 spin_unlock(&priv->lock); in pch_console_write()
1755 struct eg20t_port *priv; in pch_uart_init_port() local
1770 priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL); in pch_uart_init_port()
1771 if (priv == NULL) in pch_uart_init_port()
1793 spin_lock_init(&priv->lock); in pch_uart_init_port()
1797 priv->mapbase = mapbase; in pch_uart_init_port()
1798 priv->iobase = iobase; in pch_uart_init_port()
1799 priv->pdev = pdev; in pch_uart_init_port()
1800 priv->tx_empty = 1; in pch_uart_init_port()
1801 priv->rxbuf.buf = rxbuf; in pch_uart_init_port()
1802 priv->rxbuf.size = PAGE_SIZE; in pch_uart_init_port()
1804 priv->fifo_size = fifosize; in pch_uart_init_port()
1805 priv->uartclk = pch_uart_get_uartclk(); in pch_uart_init_port()
1806 priv->port_type = PORT_MAX_8250 + port_type + 1; in pch_uart_init_port()
1807 priv->port.dev = &pdev->dev; in pch_uart_init_port()
1808 priv->port.iobase = iobase; in pch_uart_init_port()
1809 priv->port.membase = NULL; in pch_uart_init_port()
1810 priv->port.mapbase = mapbase; in pch_uart_init_port()
1811 priv->port.irq = pdev->irq; in pch_uart_init_port()
1812 priv->port.iotype = UPIO_PORT; in pch_uart_init_port()
1813 priv->port.ops = &pch_uart_ops; in pch_uart_init_port()
1814 priv->port.flags = UPF_BOOT_AUTOCONF; in pch_uart_init_port()
1815 priv->port.fifosize = fifosize; in pch_uart_init_port()
1816 priv->port.line = board->line_no; in pch_uart_init_port()
1817 priv->trigger = PCH_UART_HAL_TRIGGER_M; in pch_uart_init_port()
1819 snprintf(priv->irq_name, IRQ_NAME_SIZE, in pch_uart_init_port()
1821 priv->port.line); in pch_uart_init_port()
1823 spin_lock_init(&priv->port.lock); in pch_uart_init_port()
1825 pci_set_drvdata(pdev, priv); in pch_uart_init_port()
1826 priv->trigger_level = 1; in pch_uart_init_port()
1827 priv->fcr = 0; in pch_uart_init_port()
1830 pch_uart_ports[board->line_no] = priv; in pch_uart_init_port()
1832 ret = uart_add_one_port(&pch_uart_driver, &priv->port); in pch_uart_init_port()
1838 priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO, in pch_uart_init_port()
1839 NULL, priv, &port_regs_ops); in pch_uart_init_port()
1842 return priv; in pch_uart_init_port()
1850 kfree(priv); in pch_uart_init_port()
1856 static void pch_uart_exit_port(struct eg20t_port *priv) in pch_uart_exit_port() argument
1860 if (priv->debugfs) in pch_uart_exit_port()
1861 debugfs_remove(priv->debugfs); in pch_uart_exit_port()
1863 uart_remove_one_port(&pch_uart_driver, &priv->port); in pch_uart_exit_port()
1864 free_page((unsigned long)priv->rxbuf.buf); in pch_uart_exit_port()
1869 struct eg20t_port *priv = pci_get_drvdata(pdev); in pch_uart_pci_remove() local
1874 pch_uart_ports[priv->port.line] = NULL; in pch_uart_pci_remove()
1876 pch_uart_exit_port(priv); in pch_uart_pci_remove()
1878 kfree(priv); in pch_uart_pci_remove()
1884 struct eg20t_port *priv = pci_get_drvdata(pdev); in pch_uart_pci_suspend() local
1886 uart_suspend_port(&pch_uart_driver, &priv->port); in pch_uart_pci_suspend()
1895 struct eg20t_port *priv = pci_get_drvdata(pdev); in pch_uart_pci_resume() local
1908 uart_resume_port(&pch_uart_driver, &priv->port); in pch_uart_pci_resume()
1947 struct eg20t_port *priv; in pch_uart_pci_probe() local
1953 priv = pch_uart_init_port(pdev, id); in pch_uart_pci_probe()
1954 if (!priv) { in pch_uart_pci_probe()
1958 pci_set_drvdata(pdev, priv); in pch_uart_pci_probe()