Lines Matching refs:readl

121 	val = readl(port->membase + UART_CR);  in netx_stop_tx()
128 val = readl(port->membase + UART_CR); in netx_stop_rx()
135 val = readl(port->membase + UART_CR); in netx_enable_ms()
164 } while (!(readl(port->membase + UART_FR) & FR_TXFF)); in netx_transmit_buffer()
173 readl(port->membase + UART_CR) | CR_TIE, port->membase + UART_CR); in netx_start_tx()
175 if (!(readl(port->membase + UART_FR) & FR_TXFF)) in netx_start_tx()
181 return readl(port->membase + UART_FR) & FR_BUSY ? 0 : TIOCSER_TEMT; in netx_tx_empty()
203 while (!(readl(port->membase + UART_FR) & FR_RXFE)) { in netx_rxint()
204 rx = readl(port->membase + UART_DR); in netx_rxint()
207 status = readl(port->membase + UART_SR); in netx_rxint()
252 status = readl(port->membase + UART_IIR) & IIR_MASK; in netx_int()
259 if (readl(port->membase + UART_FR) & FR_CTS) in netx_int()
265 status = readl(port->membase + UART_IIR) & IIR_MASK; in netx_int()
276 if (readl(port->membase + UART_FR) & FR_CTS) in netx_get_mctrl()
288 val = readl(port->membase + UART_RTS_CR); in netx_set_mctrl()
298 line_cr = readl(port->membase + UART_LINE_CR); in netx_break_ctl()
319 writel(readl(port->membase + UART_LINE_CR) | LINE_CR_FEN, in netx_startup()
382 old_cr = readl(port->membase + UART_CR); in netx_set_termios()
389 while (readl(port->membase + UART_FR) & FR_BUSY); in netx_set_termios()
531 while (readl(port->membase + UART_FR) & FR_BUSY); in netx_console_putchar()
541 cr_save = readl(port->membase + UART_CR); in netx_console_write()
546 while (readl(port->membase + UART_FR) & FR_BUSY); in netx_console_write()
556 *baud = (readl(port->membase + UART_BAUDDIV_MSB) << 8) | in netx_console_get_options()
557 readl(port->membase + UART_BAUDDIV_LSB); in netx_console_get_options()
564 line_cr = readl(port->membase + UART_LINE_CR); in netx_console_get_options()
588 if (readl(port->membase + UART_RTS_CR) & RTS_CR_AUTO) in netx_console_get_options()
616 if (readl(sport->port.membase + UART_CR) & CR_UART_EN) { in netx_console_setup()