Lines Matching refs:pi
319 static void mpsc_start_rx(struct mpsc_port_info *pi);
320 static void mpsc_free_ring_mem(struct mpsc_port_info *pi);
329 static void mpsc_brg_init(struct mpsc_port_info *pi, u32 clk_src) in mpsc_brg_init() argument
333 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR); in mpsc_brg_init()
336 if (pi->brg_can_tune) in mpsc_brg_init()
339 if (pi->mirror_regs) in mpsc_brg_init()
340 pi->BRG_BCR_m = v; in mpsc_brg_init()
341 writel(v, pi->brg_base + BRG_BCR); in mpsc_brg_init()
343 writel(readl(pi->brg_base + BRG_BTR) & 0xffff0000, in mpsc_brg_init()
344 pi->brg_base + BRG_BTR); in mpsc_brg_init()
347 static void mpsc_brg_enable(struct mpsc_port_info *pi) in mpsc_brg_enable() argument
351 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR); in mpsc_brg_enable()
354 if (pi->mirror_regs) in mpsc_brg_enable()
355 pi->BRG_BCR_m = v; in mpsc_brg_enable()
356 writel(v, pi->brg_base + BRG_BCR); in mpsc_brg_enable()
359 static void mpsc_brg_disable(struct mpsc_port_info *pi) in mpsc_brg_disable() argument
363 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR); in mpsc_brg_disable()
366 if (pi->mirror_regs) in mpsc_brg_disable()
367 pi->BRG_BCR_m = v; in mpsc_brg_disable()
368 writel(v, pi->brg_base + BRG_BCR); in mpsc_brg_disable()
380 static void mpsc_set_baudrate(struct mpsc_port_info *pi, u32 baud) in mpsc_set_baudrate() argument
382 u32 cdv = (pi->port.uartclk / (baud << 5)) - 1; in mpsc_set_baudrate()
385 mpsc_brg_disable(pi); in mpsc_set_baudrate()
386 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR); in mpsc_set_baudrate()
389 if (pi->mirror_regs) in mpsc_set_baudrate()
390 pi->BRG_BCR_m = v; in mpsc_set_baudrate()
391 writel(v, pi->brg_base + BRG_BCR); in mpsc_set_baudrate()
392 mpsc_brg_enable(pi); in mpsc_set_baudrate()
403 static void mpsc_sdma_burstsize(struct mpsc_port_info *pi, u32 burst_size) in mpsc_sdma_burstsize() argument
408 pi->port.line, burst_size); in mpsc_sdma_burstsize()
421 writel((readl(pi->sdma_base + SDMA_SDC) & (0x3 << 12)) | (v << 12), in mpsc_sdma_burstsize()
422 pi->sdma_base + SDMA_SDC); in mpsc_sdma_burstsize()
425 static void mpsc_sdma_init(struct mpsc_port_info *pi, u32 burst_size) in mpsc_sdma_init() argument
427 pr_debug("mpsc_sdma_init[%d]: burst_size: %d\n", pi->port.line, in mpsc_sdma_init()
430 writel((readl(pi->sdma_base + SDMA_SDC) & 0x3ff) | 0x03f, in mpsc_sdma_init()
431 pi->sdma_base + SDMA_SDC); in mpsc_sdma_init()
432 mpsc_sdma_burstsize(pi, burst_size); in mpsc_sdma_init()
435 static u32 mpsc_sdma_intr_mask(struct mpsc_port_info *pi, u32 mask) in mpsc_sdma_intr_mask() argument
439 pr_debug("mpsc_sdma_intr_mask[%d]: mask: 0x%x\n", pi->port.line, mask); in mpsc_sdma_intr_mask()
441 old = v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m : in mpsc_sdma_intr_mask()
442 readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK); in mpsc_sdma_intr_mask()
445 if (pi->port.line) in mpsc_sdma_intr_mask()
449 if (pi->mirror_regs) in mpsc_sdma_intr_mask()
450 pi->shared_regs->SDMA_INTR_MASK_m = v; in mpsc_sdma_intr_mask()
451 writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK); in mpsc_sdma_intr_mask()
453 if (pi->port.line) in mpsc_sdma_intr_mask()
458 static void mpsc_sdma_intr_unmask(struct mpsc_port_info *pi, u32 mask) in mpsc_sdma_intr_unmask() argument
462 pr_debug("mpsc_sdma_intr_unmask[%d]: mask: 0x%x\n", pi->port.line,mask); in mpsc_sdma_intr_unmask()
464 v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m in mpsc_sdma_intr_unmask()
465 : readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK); in mpsc_sdma_intr_unmask()
468 if (pi->port.line) in mpsc_sdma_intr_unmask()
472 if (pi->mirror_regs) in mpsc_sdma_intr_unmask()
473 pi->shared_regs->SDMA_INTR_MASK_m = v; in mpsc_sdma_intr_unmask()
474 writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK); in mpsc_sdma_intr_unmask()
477 static void mpsc_sdma_intr_ack(struct mpsc_port_info *pi) in mpsc_sdma_intr_ack() argument
479 pr_debug("mpsc_sdma_intr_ack[%d]: Acknowledging IRQ\n", pi->port.line); in mpsc_sdma_intr_ack()
481 if (pi->mirror_regs) in mpsc_sdma_intr_ack()
482 pi->shared_regs->SDMA_INTR_CAUSE_m = 0; in mpsc_sdma_intr_ack()
483 writeb(0x00, pi->shared_regs->sdma_intr_base + SDMA_INTR_CAUSE in mpsc_sdma_intr_ack()
484 + pi->port.line); in mpsc_sdma_intr_ack()
487 static void mpsc_sdma_set_rx_ring(struct mpsc_port_info *pi, in mpsc_sdma_set_rx_ring() argument
491 pi->port.line, (u32)rxre_p); in mpsc_sdma_set_rx_ring()
493 writel((u32)rxre_p, pi->sdma_base + SDMA_SCRDP); in mpsc_sdma_set_rx_ring()
496 static void mpsc_sdma_set_tx_ring(struct mpsc_port_info *pi, in mpsc_sdma_set_tx_ring() argument
499 writel((u32)txre_p, pi->sdma_base + SDMA_SFTDP); in mpsc_sdma_set_tx_ring()
500 writel((u32)txre_p, pi->sdma_base + SDMA_SCTDP); in mpsc_sdma_set_tx_ring()
503 static void mpsc_sdma_cmd(struct mpsc_port_info *pi, u32 val) in mpsc_sdma_cmd() argument
507 v = readl(pi->sdma_base + SDMA_SDCM); in mpsc_sdma_cmd()
513 writel(v, pi->sdma_base + SDMA_SDCM); in mpsc_sdma_cmd()
517 static uint mpsc_sdma_tx_active(struct mpsc_port_info *pi) in mpsc_sdma_tx_active() argument
519 return readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_TXD; in mpsc_sdma_tx_active()
522 static void mpsc_sdma_start_tx(struct mpsc_port_info *pi) in mpsc_sdma_start_tx() argument
527 if (!mpsc_sdma_tx_active(pi)) { in mpsc_sdma_start_tx()
528 txre = (struct mpsc_tx_desc *)(pi->txr in mpsc_sdma_start_tx()
529 + (pi->txr_tail * MPSC_TXRE_SIZE)); in mpsc_sdma_start_tx()
530 dma_cache_sync(pi->port.dev, (void *)txre, MPSC_TXRE_SIZE, in mpsc_sdma_start_tx()
533 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_sdma_start_tx()
540 (pi->txr_p + (pi->txr_tail * MPSC_TXRE_SIZE)); in mpsc_sdma_start_tx()
542 mpsc_sdma_set_tx_ring(pi, txre_p); in mpsc_sdma_start_tx()
543 mpsc_sdma_cmd(pi, SDMA_SDCM_STD | SDMA_SDCM_TXD); in mpsc_sdma_start_tx()
548 static void mpsc_sdma_stop(struct mpsc_port_info *pi) in mpsc_sdma_stop() argument
550 pr_debug("mpsc_sdma_stop[%d]: Stopping SDMA\n", pi->port.line); in mpsc_sdma_stop()
553 mpsc_sdma_cmd(pi, 0); in mpsc_sdma_stop()
554 mpsc_sdma_cmd(pi, SDMA_SDCM_AR | SDMA_SDCM_AT); in mpsc_sdma_stop()
557 mpsc_sdma_set_tx_ring(pi, NULL); in mpsc_sdma_stop()
558 mpsc_sdma_set_rx_ring(pi, NULL); in mpsc_sdma_stop()
561 mpsc_sdma_intr_mask(pi, 0xf); in mpsc_sdma_stop()
562 mpsc_sdma_intr_ack(pi); in mpsc_sdma_stop()
573 static void mpsc_hw_init(struct mpsc_port_info *pi) in mpsc_hw_init() argument
577 pr_debug("mpsc_hw_init[%d]: Initializing hardware\n", pi->port.line); in mpsc_hw_init()
580 if (pi->mirror_regs) { in mpsc_hw_init()
581 v = pi->shared_regs->MPSC_MRR_m; in mpsc_hw_init()
583 pi->shared_regs->MPSC_MRR_m = v; in mpsc_hw_init()
584 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR); in mpsc_hw_init()
586 v = pi->shared_regs->MPSC_RCRR_m; in mpsc_hw_init()
588 pi->shared_regs->MPSC_RCRR_m = v; in mpsc_hw_init()
589 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_RCRR); in mpsc_hw_init()
591 v = pi->shared_regs->MPSC_TCRR_m; in mpsc_hw_init()
593 pi->shared_regs->MPSC_TCRR_m = v; in mpsc_hw_init()
594 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR); in mpsc_hw_init()
596 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_MRR); in mpsc_hw_init()
598 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR); in mpsc_hw_init()
600 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_RCRR); in mpsc_hw_init()
602 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_RCRR); in mpsc_hw_init()
604 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_TCRR); in mpsc_hw_init()
606 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR); in mpsc_hw_init()
610 writel(0x000004c4, pi->mpsc_base + MPSC_MMCRL); in mpsc_hw_init()
613 writel(0x04400400, pi->mpsc_base + MPSC_MMCRH); in mpsc_hw_init()
614 mpsc_set_baudrate(pi, pi->default_baud); in mpsc_hw_init()
616 if (pi->mirror_regs) { in mpsc_hw_init()
617 pi->MPSC_CHR_1_m = 0; in mpsc_hw_init()
618 pi->MPSC_CHR_2_m = 0; in mpsc_hw_init()
620 writel(0, pi->mpsc_base + MPSC_CHR_1); in mpsc_hw_init()
621 writel(0, pi->mpsc_base + MPSC_CHR_2); in mpsc_hw_init()
622 writel(pi->mpsc_max_idle, pi->mpsc_base + MPSC_CHR_3); in mpsc_hw_init()
623 writel(0, pi->mpsc_base + MPSC_CHR_4); in mpsc_hw_init()
624 writel(0, pi->mpsc_base + MPSC_CHR_5); in mpsc_hw_init()
625 writel(0, pi->mpsc_base + MPSC_CHR_6); in mpsc_hw_init()
626 writel(0, pi->mpsc_base + MPSC_CHR_7); in mpsc_hw_init()
627 writel(0, pi->mpsc_base + MPSC_CHR_8); in mpsc_hw_init()
628 writel(0, pi->mpsc_base + MPSC_CHR_9); in mpsc_hw_init()
629 writel(0, pi->mpsc_base + MPSC_CHR_10); in mpsc_hw_init()
632 static void mpsc_enter_hunt(struct mpsc_port_info *pi) in mpsc_enter_hunt() argument
634 pr_debug("mpsc_enter_hunt[%d]: Hunting...\n", pi->port.line); in mpsc_enter_hunt()
636 if (pi->mirror_regs) { in mpsc_enter_hunt()
637 writel(pi->MPSC_CHR_2_m | MPSC_CHR_2_EH, in mpsc_enter_hunt()
638 pi->mpsc_base + MPSC_CHR_2); in mpsc_enter_hunt()
642 writel(readl(pi->mpsc_base + MPSC_CHR_2) | MPSC_CHR_2_EH, in mpsc_enter_hunt()
643 pi->mpsc_base + MPSC_CHR_2); in mpsc_enter_hunt()
645 while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_EH) in mpsc_enter_hunt()
650 static void mpsc_freeze(struct mpsc_port_info *pi) in mpsc_freeze() argument
654 pr_debug("mpsc_freeze[%d]: Freezing\n", pi->port.line); in mpsc_freeze()
656 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m : in mpsc_freeze()
657 readl(pi->mpsc_base + MPSC_MPCR); in mpsc_freeze()
660 if (pi->mirror_regs) in mpsc_freeze()
661 pi->MPSC_MPCR_m = v; in mpsc_freeze()
662 writel(v, pi->mpsc_base + MPSC_MPCR); in mpsc_freeze()
665 static void mpsc_unfreeze(struct mpsc_port_info *pi) in mpsc_unfreeze() argument
669 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m : in mpsc_unfreeze()
670 readl(pi->mpsc_base + MPSC_MPCR); in mpsc_unfreeze()
673 if (pi->mirror_regs) in mpsc_unfreeze()
674 pi->MPSC_MPCR_m = v; in mpsc_unfreeze()
675 writel(v, pi->mpsc_base + MPSC_MPCR); in mpsc_unfreeze()
677 pr_debug("mpsc_unfreeze[%d]: Unfrozen\n", pi->port.line); in mpsc_unfreeze()
680 static void mpsc_set_char_length(struct mpsc_port_info *pi, u32 len) in mpsc_set_char_length() argument
684 pr_debug("mpsc_set_char_length[%d]: char len: %d\n", pi->port.line,len); in mpsc_set_char_length()
686 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m : in mpsc_set_char_length()
687 readl(pi->mpsc_base + MPSC_MPCR); in mpsc_set_char_length()
690 if (pi->mirror_regs) in mpsc_set_char_length()
691 pi->MPSC_MPCR_m = v; in mpsc_set_char_length()
692 writel(v, pi->mpsc_base + MPSC_MPCR); in mpsc_set_char_length()
695 static void mpsc_set_stop_bit_length(struct mpsc_port_info *pi, u32 len) in mpsc_set_stop_bit_length() argument
700 pi->port.line, len); in mpsc_set_stop_bit_length()
702 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m : in mpsc_set_stop_bit_length()
703 readl(pi->mpsc_base + MPSC_MPCR); in mpsc_set_stop_bit_length()
707 if (pi->mirror_regs) in mpsc_set_stop_bit_length()
708 pi->MPSC_MPCR_m = v; in mpsc_set_stop_bit_length()
709 writel(v, pi->mpsc_base + MPSC_MPCR); in mpsc_set_stop_bit_length()
712 static void mpsc_set_parity(struct mpsc_port_info *pi, u32 p) in mpsc_set_parity() argument
716 pr_debug("mpsc_set_parity[%d]: parity bits: 0x%x\n", pi->port.line, p); in mpsc_set_parity()
718 v = (pi->mirror_regs) ? pi->MPSC_CHR_2_m : in mpsc_set_parity()
719 readl(pi->mpsc_base + MPSC_CHR_2); in mpsc_set_parity()
724 if (pi->mirror_regs) in mpsc_set_parity()
725 pi->MPSC_CHR_2_m = v; in mpsc_set_parity()
726 writel(v, pi->mpsc_base + MPSC_CHR_2); in mpsc_set_parity()
737 static void mpsc_init_hw(struct mpsc_port_info *pi) in mpsc_init_hw() argument
739 pr_debug("mpsc_init_hw[%d]: Initializing\n", pi->port.line); in mpsc_init_hw()
741 mpsc_brg_init(pi, pi->brg_clk_src); in mpsc_init_hw()
742 mpsc_brg_enable(pi); in mpsc_init_hw()
743 mpsc_sdma_init(pi, dma_get_cache_alignment()); /* burst a cacheline */ in mpsc_init_hw()
744 mpsc_sdma_stop(pi); in mpsc_init_hw()
745 mpsc_hw_init(pi); in mpsc_init_hw()
748 static int mpsc_alloc_ring_mem(struct mpsc_port_info *pi) in mpsc_alloc_ring_mem() argument
753 pi->port.line); in mpsc_alloc_ring_mem()
755 if (!pi->dma_region) { in mpsc_alloc_ring_mem()
756 if (!dma_set_mask(pi->port.dev, 0xffffffff)) { in mpsc_alloc_ring_mem()
759 } else if ((pi->dma_region = dma_alloc_noncoherent(pi->port.dev, in mpsc_alloc_ring_mem()
761 &pi->dma_region_p, GFP_KERNEL)) in mpsc_alloc_ring_mem()
771 static void mpsc_free_ring_mem(struct mpsc_port_info *pi) in mpsc_free_ring_mem() argument
773 pr_debug("mpsc_free_ring_mem[%d]: Freeing ring mem\n", pi->port.line); in mpsc_free_ring_mem()
775 if (pi->dma_region) { in mpsc_free_ring_mem()
776 dma_free_noncoherent(pi->port.dev, MPSC_DMA_ALLOC_SIZE, in mpsc_free_ring_mem()
777 pi->dma_region, pi->dma_region_p); in mpsc_free_ring_mem()
778 pi->dma_region = NULL; in mpsc_free_ring_mem()
779 pi->dma_region_p = (dma_addr_t)NULL; in mpsc_free_ring_mem()
783 static void mpsc_init_rings(struct mpsc_port_info *pi) in mpsc_init_rings() argument
791 pr_debug("mpsc_init_rings[%d]: Initializing rings\n", pi->port.line); in mpsc_init_rings()
793 BUG_ON(pi->dma_region == NULL); in mpsc_init_rings()
795 memset(pi->dma_region, 0, MPSC_DMA_ALLOC_SIZE); in mpsc_init_rings()
801 dp = ALIGN((u32)pi->dma_region, dma_get_cache_alignment()); in mpsc_init_rings()
802 dp_p = ALIGN((u32)pi->dma_region_p, dma_get_cache_alignment()); in mpsc_init_rings()
808 pi->rxr = dp; in mpsc_init_rings()
809 pi->rxr_p = dp_p; in mpsc_init_rings()
813 pi->rxb = (u8 *)dp; in mpsc_init_rings()
814 pi->rxb_p = (u8 *)dp_p; in mpsc_init_rings()
818 pi->rxr_posn = 0; in mpsc_init_rings()
820 pi->txr = dp; in mpsc_init_rings()
821 pi->txr_p = dp_p; in mpsc_init_rings()
825 pi->txb = (u8 *)dp; in mpsc_init_rings()
826 pi->txb_p = (u8 *)dp_p; in mpsc_init_rings()
828 pi->txr_head = 0; in mpsc_init_rings()
829 pi->txr_tail = 0; in mpsc_init_rings()
832 dp = pi->rxr; in mpsc_init_rings()
833 dp_p = pi->rxr_p; in mpsc_init_rings()
834 bp = pi->rxb; in mpsc_init_rings()
835 bp_p = pi->rxb_p; in mpsc_init_rings()
853 rxre->link = cpu_to_be32(pi->rxr_p); /* Wrap last back to first */ in mpsc_init_rings()
856 dp = pi->txr; in mpsc_init_rings()
857 dp_p = pi->txr_p; in mpsc_init_rings()
858 bp = pi->txb; in mpsc_init_rings()
859 bp_p = pi->txb_p; in mpsc_init_rings()
872 txre->link = cpu_to_be32(pi->txr_p); /* Wrap last back to first */ in mpsc_init_rings()
874 dma_cache_sync(pi->port.dev, (void *)pi->dma_region, in mpsc_init_rings()
877 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_init_rings()
878 flush_dcache_range((ulong)pi->dma_region, in mpsc_init_rings()
879 (ulong)pi->dma_region in mpsc_init_rings()
886 static void mpsc_uninit_rings(struct mpsc_port_info *pi) in mpsc_uninit_rings() argument
888 pr_debug("mpsc_uninit_rings[%d]: Uninitializing rings\n",pi->port.line); in mpsc_uninit_rings()
890 BUG_ON(pi->dma_region == NULL); in mpsc_uninit_rings()
892 pi->rxr = 0; in mpsc_uninit_rings()
893 pi->rxr_p = 0; in mpsc_uninit_rings()
894 pi->rxb = NULL; in mpsc_uninit_rings()
895 pi->rxb_p = NULL; in mpsc_uninit_rings()
896 pi->rxr_posn = 0; in mpsc_uninit_rings()
898 pi->txr = 0; in mpsc_uninit_rings()
899 pi->txr_p = 0; in mpsc_uninit_rings()
900 pi->txb = NULL; in mpsc_uninit_rings()
901 pi->txb_p = NULL; in mpsc_uninit_rings()
902 pi->txr_head = 0; in mpsc_uninit_rings()
903 pi->txr_tail = 0; in mpsc_uninit_rings()
906 static int mpsc_make_ready(struct mpsc_port_info *pi) in mpsc_make_ready() argument
910 pr_debug("mpsc_make_ready[%d]: Making cltr ready\n", pi->port.line); in mpsc_make_ready()
912 if (!pi->ready) { in mpsc_make_ready()
913 mpsc_init_hw(pi); in mpsc_make_ready()
914 rc = mpsc_alloc_ring_mem(pi); in mpsc_make_ready()
917 mpsc_init_rings(pi); in mpsc_make_ready()
918 pi->ready = 1; in mpsc_make_ready()
936 static int mpsc_rx_intr(struct mpsc_port_info *pi, unsigned long *flags) in mpsc_rx_intr() argument
939 struct tty_port *port = &pi->port.state->port; in mpsc_rx_intr()
945 pr_debug("mpsc_rx_intr[%d]: Handling Rx intr\n", pi->port.line); in mpsc_rx_intr()
947 rxre = (struct mpsc_rx_desc *)(pi->rxr + (pi->rxr_posn*MPSC_RXRE_SIZE)); in mpsc_rx_intr()
949 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE, in mpsc_rx_intr()
952 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_rx_intr()
972 spin_unlock_irqrestore(&pi->port.lock, *flags); in mpsc_rx_intr()
974 spin_lock_irqsave(&pi->port.lock, *flags); in mpsc_rx_intr()
982 bp = pi->rxb + (pi->rxr_posn * MPSC_RXBE_SIZE); in mpsc_rx_intr()
983 dma_cache_sync(pi->port.dev, (void *)bp, MPSC_RXBE_SIZE, in mpsc_rx_intr()
986 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_rx_intr()
1003 pi->port.icount.rx++; in mpsc_rx_intr()
1006 pi->port.icount.brk++; in mpsc_rx_intr()
1008 if (uart_handle_break(&pi->port)) in mpsc_rx_intr()
1011 pi->port.icount.frame++; in mpsc_rx_intr()
1013 pi->port.icount.overrun++; in mpsc_rx_intr()
1016 cmdstat &= pi->port.read_status_mask; in mpsc_rx_intr()
1028 if (uart_handle_sysrq_char(&pi->port, *bp)) { in mpsc_rx_intr()
1043 && !(cmdstat & pi->port.ignore_status_mask)) { in mpsc_rx_intr()
1049 pi->port.icount.rx += bytes_in; in mpsc_rx_intr()
1059 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE, in mpsc_rx_intr()
1062 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_rx_intr()
1068 pi->rxr_posn = (pi->rxr_posn + 1) & (MPSC_RXR_ENTRIES - 1); in mpsc_rx_intr()
1070 (pi->rxr + (pi->rxr_posn * MPSC_RXRE_SIZE)); in mpsc_rx_intr()
1071 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE, in mpsc_rx_intr()
1074 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_rx_intr()
1082 if ((readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_ERD) == 0) in mpsc_rx_intr()
1083 mpsc_start_rx(pi); in mpsc_rx_intr()
1085 spin_unlock_irqrestore(&pi->port.lock, *flags); in mpsc_rx_intr()
1087 spin_lock_irqsave(&pi->port.lock, *flags); in mpsc_rx_intr()
1091 static void mpsc_setup_tx_desc(struct mpsc_port_info *pi, u32 count, u32 intr) in mpsc_setup_tx_desc() argument
1095 txre = (struct mpsc_tx_desc *)(pi->txr in mpsc_setup_tx_desc()
1096 + (pi->txr_head * MPSC_TXRE_SIZE)); in mpsc_setup_tx_desc()
1105 dma_cache_sync(pi->port.dev, (void *)txre, MPSC_TXRE_SIZE, in mpsc_setup_tx_desc()
1108 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_setup_tx_desc()
1114 static void mpsc_copy_tx_data(struct mpsc_port_info *pi) in mpsc_copy_tx_data() argument
1116 struct circ_buf *xmit = &pi->port.state->xmit; in mpsc_copy_tx_data()
1121 while (CIRC_CNT(pi->txr_head, pi->txr_tail, MPSC_TXR_ENTRIES) in mpsc_copy_tx_data()
1123 if (pi->port.x_char) { in mpsc_copy_tx_data()
1132 bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE); in mpsc_copy_tx_data()
1133 *bp = pi->port.x_char; in mpsc_copy_tx_data()
1134 pi->port.x_char = 0; in mpsc_copy_tx_data()
1137 && !uart_tx_stopped(&pi->port)) { in mpsc_copy_tx_data()
1142 bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE); in mpsc_copy_tx_data()
1147 uart_write_wakeup(&pi->port); in mpsc_copy_tx_data()
1152 dma_cache_sync(pi->port.dev, (void *)bp, MPSC_TXBE_SIZE, in mpsc_copy_tx_data()
1155 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_copy_tx_data()
1159 mpsc_setup_tx_desc(pi, i, 1); in mpsc_copy_tx_data()
1162 pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1); in mpsc_copy_tx_data()
1166 static int mpsc_tx_intr(struct mpsc_port_info *pi) in mpsc_tx_intr() argument
1172 spin_lock_irqsave(&pi->tx_lock, iflags); in mpsc_tx_intr()
1174 if (!mpsc_sdma_tx_active(pi)) { in mpsc_tx_intr()
1175 txre = (struct mpsc_tx_desc *)(pi->txr in mpsc_tx_intr()
1176 + (pi->txr_tail * MPSC_TXRE_SIZE)); in mpsc_tx_intr()
1178 dma_cache_sync(pi->port.dev, (void *)txre, MPSC_TXRE_SIZE, in mpsc_tx_intr()
1181 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_tx_intr()
1188 pi->port.icount.tx += be16_to_cpu(txre->bytecnt); in mpsc_tx_intr()
1189 pi->txr_tail = (pi->txr_tail+1) & (MPSC_TXR_ENTRIES-1); in mpsc_tx_intr()
1192 if (pi->txr_head == pi->txr_tail) in mpsc_tx_intr()
1195 txre = (struct mpsc_tx_desc *)(pi->txr in mpsc_tx_intr()
1196 + (pi->txr_tail * MPSC_TXRE_SIZE)); in mpsc_tx_intr()
1197 dma_cache_sync(pi->port.dev, (void *)txre, in mpsc_tx_intr()
1200 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_tx_intr()
1206 mpsc_copy_tx_data(pi); in mpsc_tx_intr()
1207 mpsc_sdma_start_tx(pi); /* start next desc if ready */ in mpsc_tx_intr()
1210 spin_unlock_irqrestore(&pi->tx_lock, iflags); in mpsc_tx_intr()
1221 struct mpsc_port_info *pi = dev_id; in mpsc_sdma_intr() local
1225 pr_debug("mpsc_sdma_intr[%d]: SDMA Interrupt Received\n",pi->port.line); in mpsc_sdma_intr()
1227 spin_lock_irqsave(&pi->port.lock, iflags); in mpsc_sdma_intr()
1228 mpsc_sdma_intr_ack(pi); in mpsc_sdma_intr()
1229 if (mpsc_rx_intr(pi, &iflags)) in mpsc_sdma_intr()
1231 if (mpsc_tx_intr(pi)) in mpsc_sdma_intr()
1233 spin_unlock_irqrestore(&pi->port.lock, iflags); in mpsc_sdma_intr()
1235 pr_debug("mpsc_sdma_intr[%d]: SDMA Interrupt Handled\n", pi->port.line); in mpsc_sdma_intr()
1248 struct mpsc_port_info *pi = in mpsc_tx_empty() local
1253 spin_lock_irqsave(&pi->port.lock, iflags); in mpsc_tx_empty()
1254 rc = mpsc_sdma_tx_active(pi) ? 0 : TIOCSER_TEMT; in mpsc_tx_empty()
1255 spin_unlock_irqrestore(&pi->port.lock, iflags); in mpsc_tx_empty()
1267 struct mpsc_port_info *pi = in mpsc_get_mctrl() local
1271 status = (pi->mirror_regs) ? pi->MPSC_CHR_10_m in mpsc_get_mctrl()
1272 : readl(pi->mpsc_base + MPSC_CHR_10); in mpsc_get_mctrl()
1285 struct mpsc_port_info *pi = in mpsc_stop_tx() local
1290 mpsc_freeze(pi); in mpsc_stop_tx()
1295 struct mpsc_port_info *pi = in mpsc_start_tx() local
1299 spin_lock_irqsave(&pi->tx_lock, iflags); in mpsc_start_tx()
1301 mpsc_unfreeze(pi); in mpsc_start_tx()
1302 mpsc_copy_tx_data(pi); in mpsc_start_tx()
1303 mpsc_sdma_start_tx(pi); in mpsc_start_tx()
1305 spin_unlock_irqrestore(&pi->tx_lock, iflags); in mpsc_start_tx()
1310 static void mpsc_start_rx(struct mpsc_port_info *pi) in mpsc_start_rx() argument
1312 pr_debug("mpsc_start_rx[%d]: Starting...\n", pi->port.line); in mpsc_start_rx()
1314 if (pi->rcv_data) { in mpsc_start_rx()
1315 mpsc_enter_hunt(pi); in mpsc_start_rx()
1316 mpsc_sdma_cmd(pi, SDMA_SDCM_ERD); in mpsc_start_rx()
1322 struct mpsc_port_info *pi = in mpsc_stop_rx() local
1327 if (pi->mirror_regs) { in mpsc_stop_rx()
1328 writel(pi->MPSC_CHR_2_m | MPSC_CHR_2_RA, in mpsc_stop_rx()
1329 pi->mpsc_base + MPSC_CHR_2); in mpsc_stop_rx()
1333 writel(readl(pi->mpsc_base + MPSC_CHR_2) | MPSC_CHR_2_RA, in mpsc_stop_rx()
1334 pi->mpsc_base + MPSC_CHR_2); in mpsc_stop_rx()
1336 while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_RA) in mpsc_stop_rx()
1340 mpsc_sdma_cmd(pi, SDMA_SDCM_AR); in mpsc_stop_rx()
1345 struct mpsc_port_info *pi = in mpsc_break_ctl() local
1352 spin_lock_irqsave(&pi->port.lock, flags); in mpsc_break_ctl()
1353 if (pi->mirror_regs) in mpsc_break_ctl()
1354 pi->MPSC_CHR_1_m = v; in mpsc_break_ctl()
1355 writel(v, pi->mpsc_base + MPSC_CHR_1); in mpsc_break_ctl()
1356 spin_unlock_irqrestore(&pi->port.lock, flags); in mpsc_break_ctl()
1361 struct mpsc_port_info *pi = in mpsc_startup() local
1367 port->line, pi->port.irq); in mpsc_startup()
1369 if ((rc = mpsc_make_ready(pi)) == 0) { in mpsc_startup()
1371 mpsc_sdma_intr_ack(pi); in mpsc_startup()
1377 if (request_irq(pi->port.irq, mpsc_sdma_intr, flag, in mpsc_startup()
1378 "mpsc-sdma", pi)) in mpsc_startup()
1380 pi->port.irq); in mpsc_startup()
1382 mpsc_sdma_intr_unmask(pi, 0xf); in mpsc_startup()
1383 mpsc_sdma_set_rx_ring(pi, (struct mpsc_rx_desc *)(pi->rxr_p in mpsc_startup()
1384 + (pi->rxr_posn * MPSC_RXRE_SIZE))); in mpsc_startup()
1392 struct mpsc_port_info *pi = in mpsc_shutdown() local
1397 mpsc_sdma_stop(pi); in mpsc_shutdown()
1398 free_irq(pi->port.irq, pi); in mpsc_shutdown()
1404 struct mpsc_port_info *pi = in mpsc_set_termios() local
1410 pi->c_iflag = termios->c_iflag; in mpsc_set_termios()
1411 pi->c_cflag = termios->c_cflag; in mpsc_set_termios()
1449 spin_lock_irqsave(&pi->port.lock, flags); in mpsc_set_termios()
1453 mpsc_set_char_length(pi, chr_bits); in mpsc_set_termios()
1454 mpsc_set_stop_bit_length(pi, stop_bits); in mpsc_set_termios()
1455 mpsc_set_parity(pi, par); in mpsc_set_termios()
1456 mpsc_set_baudrate(pi, baud); in mpsc_set_termios()
1459 pi->port.read_status_mask = SDMA_DESC_CMDSTAT_OR; in mpsc_set_termios()
1462 pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_PE in mpsc_set_termios()
1466 pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_BR; in mpsc_set_termios()
1469 pi->port.ignore_status_mask = 0; in mpsc_set_termios()
1472 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_PE in mpsc_set_termios()
1476 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_BR; in mpsc_set_termios()
1479 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_OR; in mpsc_set_termios()
1483 if (!pi->rcv_data) { in mpsc_set_termios()
1484 pi->rcv_data = 1; in mpsc_set_termios()
1485 mpsc_start_rx(pi); in mpsc_set_termios()
1487 } else if (pi->rcv_data) { in mpsc_set_termios()
1489 pi->rcv_data = 0; in mpsc_set_termios()
1492 spin_unlock_irqrestore(&pi->port.lock, flags); in mpsc_set_termios()
1509 struct mpsc_port_info *pi = in mpsc_release_port() local
1512 if (pi->ready) { in mpsc_release_port()
1513 mpsc_uninit_rings(pi); in mpsc_release_port()
1514 mpsc_free_ring_mem(pi); in mpsc_release_port()
1515 pi->ready = 0; in mpsc_release_port()
1525 struct mpsc_port_info *pi = in mpsc_verify_port() local
1529 pr_debug("mpsc_verify_port[%d]: Verifying port data\n", pi->port.line); in mpsc_verify_port()
1533 else if (pi->port.irq != ser->irq) in mpsc_verify_port()
1537 else if (pi->port.uartclk / 16 != ser->baud_base) /* Not sure */ in mpsc_verify_port()
1539 else if ((void *)pi->port.mapbase != ser->iomem_base) in mpsc_verify_port()
1541 else if (pi->port.iobase != ser->port) in mpsc_verify_port()
1561 struct mpsc_port_info *pi = in mpsc_get_poll_char() local
1570 pr_debug("mpsc_rx_intr[%d]: Handling Rx intr\n", pi->port.line); in mpsc_get_poll_char()
1580 rxre = (struct mpsc_rx_desc *)(pi->rxr + in mpsc_get_poll_char()
1581 (pi->rxr_posn*MPSC_RXRE_SIZE)); in mpsc_get_poll_char()
1582 dma_cache_sync(pi->port.dev, (void *)rxre, in mpsc_get_poll_char()
1585 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_get_poll_char()
1597 bp = pi->rxb + (pi->rxr_posn * MPSC_RXBE_SIZE); in mpsc_get_poll_char()
1598 dma_cache_sync(pi->port.dev, (void *) bp, in mpsc_get_poll_char()
1601 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_get_poll_char()
1607 !(cmdstat & pi->port.ignore_status_mask)) { in mpsc_get_poll_char()
1615 pi->port.icount.rx += bytes_in; in mpsc_get_poll_char()
1624 dma_cache_sync(pi->port.dev, (void *)rxre, in mpsc_get_poll_char()
1627 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_get_poll_char()
1633 pi->rxr_posn = (pi->rxr_posn + 1) & in mpsc_get_poll_char()
1635 rxre = (struct mpsc_rx_desc *)(pi->rxr + in mpsc_get_poll_char()
1636 (pi->rxr_posn * MPSC_RXRE_SIZE)); in mpsc_get_poll_char()
1637 dma_cache_sync(pi->port.dev, (void *)rxre, in mpsc_get_poll_char()
1640 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_get_poll_char()
1647 if ((readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_ERD) == 0) in mpsc_get_poll_char()
1648 mpsc_start_rx(pi); in mpsc_get_poll_char()
1662 struct mpsc_port_info *pi = in mpsc_put_poll_char() local
1666 data = readl(pi->mpsc_base + MPSC_MPCR); in mpsc_put_poll_char()
1667 writeb(c, pi->mpsc_base + MPSC_CHR_1); in mpsc_put_poll_char()
1669 data = readl(pi->mpsc_base + MPSC_CHR_2); in mpsc_put_poll_char()
1671 writel(data, pi->mpsc_base + MPSC_CHR_2); in mpsc_put_poll_char()
1674 while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_TTCS); in mpsc_put_poll_char()
1711 struct mpsc_port_info *pi = &mpsc_ports[co->index]; in mpsc_console_write() local
1716 spin_lock_irqsave(&pi->tx_lock, iflags); in mpsc_console_write()
1718 while (pi->txr_head != pi->txr_tail) { in mpsc_console_write()
1719 while (mpsc_sdma_tx_active(pi)) in mpsc_console_write()
1721 mpsc_sdma_intr_ack(pi); in mpsc_console_write()
1722 mpsc_tx_intr(pi); in mpsc_console_write()
1725 while (mpsc_sdma_tx_active(pi)) in mpsc_console_write()
1729 bp = dp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE); in mpsc_console_write()
1750 dma_cache_sync(pi->port.dev, (void *)bp, MPSC_TXBE_SIZE, in mpsc_console_write()
1753 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_console_write()
1757 mpsc_setup_tx_desc(pi, i, 0); in mpsc_console_write()
1758 pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1); in mpsc_console_write()
1759 mpsc_sdma_start_tx(pi); in mpsc_console_write()
1761 while (mpsc_sdma_tx_active(pi)) in mpsc_console_write()
1764 pi->txr_tail = (pi->txr_tail + 1) & (MPSC_TXR_ENTRIES - 1); in mpsc_console_write()
1767 spin_unlock_irqrestore(&pi->tx_lock, iflags); in mpsc_console_write()
1772 struct mpsc_port_info *pi; in mpsc_console_setup() local
1780 pi = &mpsc_ports[co->index]; in mpsc_console_setup()
1782 baud = pi->default_baud; in mpsc_console_setup()
1783 bits = pi->default_bits; in mpsc_console_setup()
1784 parity = pi->default_parity; in mpsc_console_setup()
1785 flow = pi->default_flow; in mpsc_console_setup()
1787 if (!pi->port.ops) in mpsc_console_setup()
1790 spin_lock_init(&pi->port.lock); /* Temporary fix--copied from 8250.c */ in mpsc_console_setup()
1795 return uart_set_options(&pi->port, co, baud, parity, bits, flow); in mpsc_console_setup()
1959 static int mpsc_drv_map_regs(struct mpsc_port_info *pi, in mpsc_drv_map_regs() argument
1967 pi->mpsc_base = ioremap(r->start, MPSC_REG_BLOCK_SIZE); in mpsc_drv_map_regs()
1968 pi->mpsc_base_p = r->start; in mpsc_drv_map_regs()
1978 pi->sdma_base = ioremap(r->start,MPSC_SDMA_REG_BLOCK_SIZE); in mpsc_drv_map_regs()
1979 pi->sdma_base_p = r->start; in mpsc_drv_map_regs()
1982 if (pi->mpsc_base) { in mpsc_drv_map_regs()
1983 iounmap(pi->mpsc_base); in mpsc_drv_map_regs()
1984 pi->mpsc_base = NULL; in mpsc_drv_map_regs()
1992 pi->brg_base = ioremap(r->start, MPSC_BRG_REG_BLOCK_SIZE); in mpsc_drv_map_regs()
1993 pi->brg_base_p = r->start; in mpsc_drv_map_regs()
1996 if (pi->mpsc_base) { in mpsc_drv_map_regs()
1997 iounmap(pi->mpsc_base); in mpsc_drv_map_regs()
1998 pi->mpsc_base = NULL; in mpsc_drv_map_regs()
2000 if (pi->sdma_base) { in mpsc_drv_map_regs()
2001 iounmap(pi->sdma_base); in mpsc_drv_map_regs()
2002 pi->sdma_base = NULL; in mpsc_drv_map_regs()
2012 static void mpsc_drv_unmap_regs(struct mpsc_port_info *pi) in mpsc_drv_unmap_regs() argument
2014 if (!pi->mpsc_base) { in mpsc_drv_unmap_regs()
2015 iounmap(pi->mpsc_base); in mpsc_drv_unmap_regs()
2016 release_mem_region(pi->mpsc_base_p, MPSC_REG_BLOCK_SIZE); in mpsc_drv_unmap_regs()
2018 if (!pi->sdma_base) { in mpsc_drv_unmap_regs()
2019 iounmap(pi->sdma_base); in mpsc_drv_unmap_regs()
2020 release_mem_region(pi->sdma_base_p, MPSC_SDMA_REG_BLOCK_SIZE); in mpsc_drv_unmap_regs()
2022 if (!pi->brg_base) { in mpsc_drv_unmap_regs()
2023 iounmap(pi->brg_base); in mpsc_drv_unmap_regs()
2024 release_mem_region(pi->brg_base_p, MPSC_BRG_REG_BLOCK_SIZE); in mpsc_drv_unmap_regs()
2027 pi->mpsc_base = NULL; in mpsc_drv_unmap_regs()
2028 pi->sdma_base = NULL; in mpsc_drv_unmap_regs()
2029 pi->brg_base = NULL; in mpsc_drv_unmap_regs()
2031 pi->mpsc_base_p = 0; in mpsc_drv_unmap_regs()
2032 pi->sdma_base_p = 0; in mpsc_drv_unmap_regs()
2033 pi->brg_base_p = 0; in mpsc_drv_unmap_regs()
2036 static void mpsc_drv_get_platform_data(struct mpsc_port_info *pi, in mpsc_drv_get_platform_data() argument
2043 pi->port.uartclk = pdata->brg_clk_freq; in mpsc_drv_get_platform_data()
2044 pi->port.iotype = UPIO_MEM; in mpsc_drv_get_platform_data()
2045 pi->port.line = num; in mpsc_drv_get_platform_data()
2046 pi->port.type = PORT_MPSC; in mpsc_drv_get_platform_data()
2047 pi->port.fifosize = MPSC_TXBE_SIZE; in mpsc_drv_get_platform_data()
2048 pi->port.membase = pi->mpsc_base; in mpsc_drv_get_platform_data()
2049 pi->port.mapbase = (ulong)pi->mpsc_base; in mpsc_drv_get_platform_data()
2050 pi->port.ops = &mpsc_pops; in mpsc_drv_get_platform_data()
2052 pi->mirror_regs = pdata->mirror_regs; in mpsc_drv_get_platform_data()
2053 pi->cache_mgmt = pdata->cache_mgmt; in mpsc_drv_get_platform_data()
2054 pi->brg_can_tune = pdata->brg_can_tune; in mpsc_drv_get_platform_data()
2055 pi->brg_clk_src = pdata->brg_clk_src; in mpsc_drv_get_platform_data()
2056 pi->mpsc_max_idle = pdata->max_idle; in mpsc_drv_get_platform_data()
2057 pi->default_baud = pdata->default_baud; in mpsc_drv_get_platform_data()
2058 pi->default_bits = pdata->default_bits; in mpsc_drv_get_platform_data()
2059 pi->default_parity = pdata->default_parity; in mpsc_drv_get_platform_data()
2060 pi->default_flow = pdata->default_flow; in mpsc_drv_get_platform_data()
2063 pi->MPSC_CHR_1_m = pdata->chr_1_val; in mpsc_drv_get_platform_data()
2064 pi->MPSC_CHR_2_m = pdata->chr_2_val; in mpsc_drv_get_platform_data()
2065 pi->MPSC_CHR_10_m = pdata->chr_10_val; in mpsc_drv_get_platform_data()
2066 pi->MPSC_MPCR_m = pdata->mpcr_val; in mpsc_drv_get_platform_data()
2067 pi->BRG_BCR_m = pdata->bcr_val; in mpsc_drv_get_platform_data()
2069 pi->shared_regs = &mpsc_shared_regs; in mpsc_drv_get_platform_data()
2071 pi->port.irq = platform_get_irq(pd, 0); in mpsc_drv_get_platform_data()
2076 struct mpsc_port_info *pi; in mpsc_drv_probe() local
2082 pi = &mpsc_ports[dev->id]; in mpsc_drv_probe()
2084 rc = mpsc_drv_map_regs(pi, dev); in mpsc_drv_probe()
2086 mpsc_drv_get_platform_data(pi, dev, dev->id); in mpsc_drv_probe()
2087 pi->port.dev = &dev->dev; in mpsc_drv_probe()
2089 rc = mpsc_make_ready(pi); in mpsc_drv_probe()
2091 spin_lock_init(&pi->tx_lock); in mpsc_drv_probe()
2092 rc = uart_add_one_port(&mpsc_reg, &pi->port); in mpsc_drv_probe()
2097 pi); in mpsc_drv_probe()
2098 mpsc_drv_unmap_regs(pi); in mpsc_drv_probe()
2101 mpsc_drv_unmap_regs(pi); in mpsc_drv_probe()