183 	out_be32(&PSC(port)->sicr, val);  in mpc52xx_psc_set_sicr()
432 	out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE);  in mpc512x_psc_fifo_init()
433 	out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);  in mpc512x_psc_fifo_init()
434 	out_be32(&FIFO_512x(port)->txalarm, 1);  in mpc512x_psc_fifo_init()
435 	out_be32(&FIFO_512x(port)->tximr, 0);  in mpc512x_psc_fifo_init()
437 	out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE);  in mpc512x_psc_fifo_init()
438 	out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);  in mpc512x_psc_fifo_init()
439 	out_be32(&FIFO_512x(port)->rxalarm, 1);  in mpc512x_psc_fifo_init()
440 	out_be32(&FIFO_512x(port)->rximr, 0);  in mpc512x_psc_fifo_init()
442 	out_be32(&FIFO_512x(port)->tximr, MPC512x_PSC_FIFO_ALARM);  in mpc512x_psc_fifo_init()
443 	out_be32(&FIFO_512x(port)->rximr, MPC512x_PSC_FIFO_ALARM);  in mpc512x_psc_fifo_init()
482 	out_be32(&FIFO_512x(port)->rximr, rx_fifo_imr);  in mpc512x_psc_stop_rx()
491 	out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);  in mpc512x_psc_start_tx()
500 	out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);  in mpc512x_psc_stop_tx()
505 	out_be32(&FIFO_512x(port)->rxisr, in_be32(&FIFO_512x(port)->rxisr));  in mpc512x_psc_rx_clr_irq()
510 	out_be32(&FIFO_512x(port)->txisr, in_be32(&FIFO_512x(port)->txisr));  in mpc512x_psc_tx_clr_irq()
528 	out_be32(&FIFO_512x(port)->tximr, 0);  in mpc512x_psc_cw_disable_ints()
529 	out_be32(&FIFO_512x(port)->rximr, 0);  in mpc512x_psc_cw_disable_ints()
534 	out_be32(&FIFO_512x(port)->tximr,  in mpc512x_psc_cw_restore_ints()
536 	out_be32(&FIFO_512x(port)->rximr, port->read_status_mask & 0x7f);  in mpc512x_psc_cw_restore_ints()
776 	out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE);  in mpc5125_psc_fifo_init()
777 	out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);  in mpc5125_psc_fifo_init()
778 	out_be32(&FIFO_5125(port)->txalarm, 1);  in mpc5125_psc_fifo_init()
779 	out_be32(&FIFO_5125(port)->tximr, 0);  in mpc5125_psc_fifo_init()
781 	out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE);  in mpc5125_psc_fifo_init()
782 	out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);  in mpc5125_psc_fifo_init()
783 	out_be32(&FIFO_5125(port)->rxalarm, 1);  in mpc5125_psc_fifo_init()
784 	out_be32(&FIFO_5125(port)->rximr, 0);  in mpc5125_psc_fifo_init()
786 	out_be32(&FIFO_5125(port)->tximr, MPC512x_PSC_FIFO_ALARM);  in mpc5125_psc_fifo_init()
787 	out_be32(&FIFO_5125(port)->rximr, MPC512x_PSC_FIFO_ALARM);  in mpc5125_psc_fifo_init()
823 	out_be32(&FIFO_5125(port)->rximr, rx_fifo_imr);  in mpc5125_psc_stop_rx()
832 	out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr);  in mpc5125_psc_start_tx()
841 	out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr);  in mpc5125_psc_stop_tx()
846 	out_be32(&FIFO_5125(port)->rxisr, in_be32(&FIFO_5125(port)->rxisr));  in mpc5125_psc_rx_clr_irq()
851 	out_be32(&FIFO_5125(port)->txisr, in_be32(&FIFO_5125(port)->txisr));  in mpc5125_psc_tx_clr_irq()
869 	out_be32(&FIFO_5125(port)->tximr, 0);  in mpc5125_psc_cw_disable_ints()
870 	out_be32(&FIFO_5125(port)->rximr, 0);  in mpc5125_psc_cw_disable_ints()
875 	out_be32(&FIFO_5125(port)->tximr,  in mpc5125_psc_cw_restore_ints()
877 	out_be32(&FIFO_5125(port)->rximr, port->read_status_mask & 0x7f);  in mpc5125_psc_cw_restore_ints()
959 	out_be32(&PSC_5125(port)->sicr, val);  in mpc5125_psc_set_sicr()