134 	out_8(&psc->ctur, divisor >> 8);  in mpc52xx_set_divisor()
135 	out_8(&psc->ctlr, divisor & 0xff);  in mpc52xx_set_divisor()
150 	out_8(&PSC(port)->command, cmd);  in mpc52xx_psc_command()
155 	out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1);  in mpc52xx_psc_set_mode()
156 	out_8(&PSC(port)->mode, mr1);  in mpc52xx_psc_set_mode()
157 	out_8(&PSC(port)->mode, mr2);  in mpc52xx_psc_set_mode()
163 		out_8(&PSC(port)->op1, MPC52xx_PSC_OP_RTS);  in mpc52xx_psc_set_rts()
165 		out_8(&PSC(port)->op0, MPC52xx_PSC_OP_RTS);  in mpc52xx_psc_set_rts()
175 	out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD);  in mpc52xx_psc_enable_ms()
193 	out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1);  in mpc52xx_psc_get_mr1()
204 	out_8(&fifo->rfcntl, 0x00);  in mpc52xx_psc_fifo_init()
206 	out_8(&fifo->tfcntl, 0x07);  in mpc52xx_psc_fifo_init()
275 	out_8(&PSC(port)->mpc52xx_psc_buffer_8, c);  in mpc52xx_psc_write_char()
515 	out_8(&FIFO_512x(port)->txdata_8, c);  in mpc512x_psc_write_char()
774 	out_8(&PSC_5125(port)->mpc52xx_psc_clock_select, 0xdd);  in mpc5125_psc_fifo_init()
856 	out_8(&FIFO_5125(port)->txdata_8, c);  in mpc5125_psc_write_char()
884 	out_8(&psc->mpc52xx_psc_clock_select, prescaler);  in mpc5125_set_divisor()
885 	out_8(&psc->ctur, divisor >> 8);  in mpc5125_set_divisor()
886 	out_8(&psc->ctlr, divisor & 0xff);  in mpc5125_set_divisor()
927 	out_8(&PSC_5125(port)->command, cmd);  in mpc5125_psc_command()
932 	out_8(&PSC_5125(port)->mr1, mr1);  in mpc5125_psc_set_mode()
933 	out_8(&PSC_5125(port)->mr2, mr2);  in mpc5125_psc_set_mode()
939 		out_8(&PSC_5125(port)->op1, MPC52xx_PSC_OP_RTS);  in mpc5125_psc_set_rts()
941 		out_8(&PSC_5125(port)->op0, MPC52xx_PSC_OP_RTS);  in mpc5125_psc_set_rts()
951 	out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD);  in mpc5125_psc_enable_ms()