Lines Matching refs:ch_cls_uart
63 u8 lcrb = readb(&ch->ch_cls_uart->lcr); in cls_set_cts_flow_control()
64 u8 ier = readb(&ch->ch_cls_uart->ier); in cls_set_cts_flow_control()
71 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_set_cts_flow_control()
73 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); in cls_set_cts_flow_control()
79 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_set_cts_flow_control()
82 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_set_cts_flow_control()
90 writeb(ier, &ch->ch_cls_uart->ier); in cls_set_cts_flow_control()
93 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); in cls_set_cts_flow_control()
97 &ch->ch_cls_uart->isr_fcr); in cls_set_cts_flow_control()
104 u8 lcrb = readb(&ch->ch_cls_uart->lcr); in cls_set_ixon_flow_control()
105 u8 ier = readb(&ch->ch_cls_uart->ier); in cls_set_ixon_flow_control()
112 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_set_ixon_flow_control()
114 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); in cls_set_ixon_flow_control()
120 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_set_ixon_flow_control()
123 writeb(ch->ch_startc, &ch->ch_cls_uart->mcr); in cls_set_ixon_flow_control()
124 writeb(0, &ch->ch_cls_uart->lsr); in cls_set_ixon_flow_control()
125 writeb(ch->ch_stopc, &ch->ch_cls_uart->msr); in cls_set_ixon_flow_control()
126 writeb(0, &ch->ch_cls_uart->spr); in cls_set_ixon_flow_control()
129 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_set_ixon_flow_control()
137 writeb(ier, &ch->ch_cls_uart->ier); in cls_set_ixon_flow_control()
140 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); in cls_set_ixon_flow_control()
144 &ch->ch_cls_uart->isr_fcr); in cls_set_ixon_flow_control()
149 u8 lcrb = readb(&ch->ch_cls_uart->lcr); in cls_set_no_output_flow_control()
150 u8 ier = readb(&ch->ch_cls_uart->ier); in cls_set_no_output_flow_control()
157 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_set_no_output_flow_control()
159 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); in cls_set_no_output_flow_control()
165 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_set_no_output_flow_control()
168 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_set_no_output_flow_control()
176 writeb(ier, &ch->ch_cls_uart->ier); in cls_set_no_output_flow_control()
179 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); in cls_set_no_output_flow_control()
183 &ch->ch_cls_uart->isr_fcr); in cls_set_no_output_flow_control()
192 u8 lcrb = readb(&ch->ch_cls_uart->lcr); in cls_set_rts_flow_control()
193 u8 ier = readb(&ch->ch_cls_uart->ier); in cls_set_rts_flow_control()
200 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_set_rts_flow_control()
202 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); in cls_set_rts_flow_control()
208 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_set_rts_flow_control()
211 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_set_rts_flow_control()
215 writeb(ier, &ch->ch_cls_uart->ier); in cls_set_rts_flow_control()
218 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); in cls_set_rts_flow_control()
222 &ch->ch_cls_uart->isr_fcr); in cls_set_rts_flow_control()
230 u8 lcrb = readb(&ch->ch_cls_uart->lcr); in cls_set_ixoff_flow_control()
231 u8 ier = readb(&ch->ch_cls_uart->ier); in cls_set_ixoff_flow_control()
238 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_set_ixoff_flow_control()
240 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); in cls_set_ixoff_flow_control()
246 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_set_ixoff_flow_control()
249 writeb(ch->ch_startc, &ch->ch_cls_uart->mcr); in cls_set_ixoff_flow_control()
250 writeb(0, &ch->ch_cls_uart->lsr); in cls_set_ixoff_flow_control()
251 writeb(ch->ch_stopc, &ch->ch_cls_uart->msr); in cls_set_ixoff_flow_control()
252 writeb(0, &ch->ch_cls_uart->spr); in cls_set_ixoff_flow_control()
255 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_set_ixoff_flow_control()
259 writeb(ier, &ch->ch_cls_uart->ier); in cls_set_ixoff_flow_control()
262 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); in cls_set_ixoff_flow_control()
266 &ch->ch_cls_uart->isr_fcr); in cls_set_ixoff_flow_control()
271 u8 lcrb = readb(&ch->ch_cls_uart->lcr); in cls_set_no_input_flow_control()
272 u8 ier = readb(&ch->ch_cls_uart->ier); in cls_set_no_input_flow_control()
279 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_set_no_input_flow_control()
281 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); in cls_set_no_input_flow_control()
287 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_set_no_input_flow_control()
290 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_set_no_input_flow_control()
294 writeb(ier, &ch->ch_cls_uart->ier); in cls_set_no_input_flow_control()
297 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); in cls_set_no_input_flow_control()
301 &ch->ch_cls_uart->isr_fcr); in cls_set_no_input_flow_control()
322 u8 temp = readb(&ch->ch_cls_uart->lcr); in cls_clear_break()
324 writeb((temp & ~UART_LCR_SBC), &ch->ch_cls_uart->lcr); in cls_clear_break()
336 u8 tmp = readb(&ch->ch_cls_uart->ier); in cls_disable_receiver()
339 writeb(tmp, &ch->ch_cls_uart->ier); in cls_disable_receiver()
344 u8 tmp = readb(&ch->ch_cls_uart->ier); in cls_enable_receiver()
347 writeb(tmp, &ch->ch_cls_uart->ier); in cls_enable_receiver()
356 writeb(ch->ch_mostat, &ch->ch_cls_uart->mcr); in cls_assert_modem_signals()
398 linestatus = readb(&ch->ch_cls_uart->lsr); in cls_copy_data_from_uart_to_queue()
412 discard = readb(&ch->ch_cls_uart->txrx); in cls_copy_data_from_uart_to_queue()
433 ch->ch_rqueue[head] = readb(&ch->ch_cls_uart->txrx); in cls_copy_data_from_uart_to_queue()
493 writeb(circ->buf[tail], &ch->ch_cls_uart->txrx); in cls_copy_data_from_queue_to_uart()
582 isr = readb(&ch->ch_cls_uart->isr_fcr); in cls_parse_isr()
611 cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr)); in cls_parse_isr()
625 &ch->ch_cls_uart->isr_fcr); in cls_flush_uart_write()
629 tmp = readb(&ch->ch_cls_uart->isr_fcr); in cls_flush_uart_write()
668 writeb(ch->ch_startc, &ch->ch_cls_uart->txrx); in cls_send_start_character()
679 writeb(ch->ch_stopc, &ch->ch_cls_uart->txrx); in cls_send_stop_character()
767 ier = readb(&ch->ch_cls_uart->ier); in cls_param()
768 uart_lcr = readb(&ch->ch_cls_uart->lcr); in cls_param()
773 writeb(UART_LCR_DLAB, &ch->ch_cls_uart->lcr); in cls_param()
774 writeb((quot & 0xff), &ch->ch_cls_uart->txrx); in cls_param()
775 writeb((quot >> 8), &ch->ch_cls_uart->ier); in cls_param()
776 writeb(lcr, &ch->ch_cls_uart->lcr); in cls_param()
780 writeb(lcr, &ch->ch_cls_uart->lcr); in cls_param()
787 writeb(ier, &ch->ch_cls_uart->ier); in cls_param()
822 cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr)); in cls_param()
870 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr); in cls_uart_init()
873 writeb(0, &ch->ch_cls_uart->ier); in cls_uart_init()
879 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_uart_init()
881 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); in cls_uart_init()
886 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_uart_init()
889 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_uart_init()
892 readb(&ch->ch_cls_uart->txrx); in cls_uart_init()
895 &ch->ch_cls_uart->isr_fcr); in cls_uart_init()
900 readb(&ch->ch_cls_uart->lsr); in cls_uart_init()
901 readb(&ch->ch_cls_uart->msr); in cls_uart_init()
910 writeb(0, &ch->ch_cls_uart->ier); in cls_uart_off()
922 u8 lsr = readb(&ch->ch_cls_uart->lsr); in cls_get_uart_bytes_left()
945 u8 temp = readb(&ch->ch_cls_uart->lcr); in cls_send_break()
947 writeb((temp | UART_LCR_SBC), &ch->ch_cls_uart->lcr); in cls_send_break()
961 writeb(c, &ch->ch_cls_uart->txrx); in cls_send_immediate_char()