Lines Matching refs:USR2
56 #define USR2 0x98 /* Status Register 2 */ macro
376 readl(port->membase + USR2) & USR2_TXDC) { in imx_stop_tx()
655 while (readl(sport->port.membase + USR2) & USR2_RDR) { in imx_rxint()
661 temp = readl(sport->port.membase + USR2); in imx_rxint()
663 writel(USR2_BRCD, sport->port.membase + USR2); in imx_rxint()
728 temp = readl(sport->port.membase + USR2); in imx_dma_rxint()
755 sts2 = readl(sport->port.membase + USR2); in imx_int()
778 writel(USR2_ORE, sport->port.membase + USR2); in imx_int()
792 ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; in imx_tx_empty()
932 if (readl(sport->port.membase + USR2) & USR2_RDR) in dma_rx_callback()
1149 writel(USR2_ORE, sport->port.membase + USR2); in imx_startup()
1387 while (!(readl(sport->port.membase + USR2) & USR2_TXDC)) in imx_set_termios()
1527 if (!(readl_relaxed(port->membase + USR2) & USR2_RDR)) in imx_poll_get_char()
1547 status = readl_relaxed(port->membase + USR2); in imx_poll_put_char()
1670 while (!(readl(sport->port.membase + USR2) & USR2_TXDC)); in imx_console_write()