50 #define UCR1  0x80 /* Control Register 1 */  macro
296 	ucr->ucr1 = readl(port->membase + UCR1);  in imx_port_ucrs_save()
305 	writel(ucr->ucr1, port->membase + UCR1);  in imx_port_ucrs_restore()
371 	temp = readl(port->membase + UCR1);  in imx_stop_tx()
372 	writel(temp & ~UCR1_TXMPTYEN, port->membase + UCR1);  in imx_stop_tx()
411 	temp = readl(sport->port.membase + UCR1);  in imx_stop_rx()
412 	writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1);  in imx_stop_rx()
449 		temp = readl(sport->port.membase + UCR1);  in imx_transmit_buffer()
453 			writel(temp, sport->port.membase + UCR1);  in imx_transmit_buffer()
455 			writel(temp, sport->port.membase + UCR1);  in imx_transmit_buffer()
488 	temp = readl(sport->port.membase + UCR1);  in dma_tx_callback()
490 	writel(temp, sport->port.membase + UCR1);  in dma_tx_callback()
562 	temp = readl(sport->port.membase + UCR1);  in imx_dma_tx()
564 	writel(temp, sport->port.membase + UCR1);  in imx_dma_tx()
596 		temp = readl(sport->port.membase + UCR1);  in imx_start_tx()
597 		writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);  in imx_start_tx()
604 			temp = readl(sport->port.membase + UCR1);  in imx_start_tx()
607 			writel(temp, sport->port.membase + UCR1);  in imx_start_tx()
733 		temp = readl(sport->port.membase + UCR1);  in imx_dma_rxint()
735 		writel(temp, sport->port.membase + UCR1);  in imx_dma_rxint()
765 	     readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) ||  in imx_int()
850 	temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;  in imx_break_ctl()
855 	writel(temp, sport->port.membase + UCR1);  in imx_break_ctl()
869 	temp = readl(sport->port.membase + UCR1);  in imx_rx_dma_done()
871 	writel(temp, sport->port.membase + UCR1);  in imx_rx_dma_done()
1066 	temp = readl(sport->port.membase + UCR1);  in imx_enable_dma()
1068 	writel(temp, sport->port.membase + UCR1);  in imx_enable_dma()
1084 	temp = readl(sport->port.membase + UCR1);  in imx_disable_dma()
1086 	writel(temp, sport->port.membase + UCR1);  in imx_disable_dma()
1154 	temp = readl(sport->port.membase + UCR1);  in imx_startup()
1157 	writel(temp, sport->port.membase + UCR1);  in imx_startup()
1226 	temp = readl(sport->port.membase + UCR1);  in imx_shutdown()
1229 	writel(temp, sport->port.membase + UCR1);  in imx_shutdown()
1251 		temp = readl(sport->port.membase + UCR1);  in imx_flush_buffer()
1253 		writel(temp, sport->port.membase + UCR1);  in imx_flush_buffer()
1383 	old_ucr1 = readl(sport->port.membase + UCR1);  in imx_set_termios()
1385 			sport->port.membase + UCR1);  in imx_set_termios()
1432 	writel(old_ucr1, sport->port.membase + UCR1);  in imx_set_termios()
1509 	temp = readl(sport->port.membase + UCR1);  in imx_poll_init()
1514 	writel(temp, sport->port.membase + UCR1);  in imx_poll_init()
1660 	writel(ucr1, sport->port.membase + UCR1);  in imx_console_write()
1690 	if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {  in imx_console_get_options()
1973 	reg = readl_relaxed(sport->port.membase + UCR1);  in serial_imx_probe()
1976 	writel_relaxed(reg, sport->port.membase + UCR1);  in serial_imx_probe()
2026 	writel(sport->saved_reg[0], sport->port.membase + UCR1);  in serial_imx_restore_context()
2036 	sport->saved_reg[0] = readl(sport->port.membase + UCR1);  in serial_imx_save_context()
2060 	val = readl(sport->port.membase + UCR1);  in serial_imx_enable_wakeup()
2065 	writel(val, sport->port.membase + UCR1);  in serial_imx_enable_wakeup()