184 #define SER_RXD_MASK         IO_MASK(R_SERIAL0_STATUS, rxd)
185 #define SER_DATA_AVAIL_MASK  IO_MASK(R_SERIAL0_STATUS, data_avail)
186 #define SER_FRAMING_ERR_MASK IO_MASK(R_SERIAL0_STATUS, framing_err)
187 #define SER_PAR_ERR_MASK     IO_MASK(R_SERIAL0_STATUS, par_err)
188 #define SER_OVERRUN_MASK     IO_MASK(R_SERIAL0_STATUS, overrun)
214 | IO_MASK(R_IRQ_MASK1_RD, ser0_data) | IO_MASK(R_IRQ_MASK1_RD, ser0_ready)
217 | IO_MASK(R_IRQ_MASK1_RD, ser1_data) | IO_MASK(R_IRQ_MASK1_RD, ser1_ready)
220 | IO_MASK(R_IRQ_MASK1_RD, ser2_data) | IO_MASK(R_IRQ_MASK1_RD, ser2_ready)
223 | IO_MASK(R_IRQ_MASK1_RD, ser3_data) | IO_MASK(R_IRQ_MASK1_RD, ser3_ready)
1086 		(info->rx_ctrl &= ~IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));  in e100_disable_rx()
1094 		(info->rx_ctrl |= IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));  in e100_enable_rx()
1149 		if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma6)) ==  in e100_disable_txdma_channel()
1151 			genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma6);  in e100_disable_txdma_channel()
1155 		if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma8)) ==  in e100_disable_txdma_channel()
1157 			genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma8);  in e100_disable_txdma_channel()
1161 		if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma2)) ==  in e100_disable_txdma_channel()
1163 			genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma2);  in e100_disable_txdma_channel()
1167 		if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma4)) ==  in e100_disable_txdma_channel()
1169 			genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma4);  in e100_disable_txdma_channel()
1186 		genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma6);  in e100_enable_txdma_channel()
1189 		genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma8);  in e100_enable_txdma_channel()
1192 		genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma2);  in e100_enable_txdma_channel()
1195 		genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma4);  in e100_enable_txdma_channel()
1211 		if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma7)) ==  in e100_disable_rxdma_channel()
1213 			genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma7);  in e100_disable_rxdma_channel()
1217 		if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma9)) ==  in e100_disable_rxdma_channel()
1219 			genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma9);  in e100_disable_rxdma_channel()
1223 		if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma3)) ==  in e100_disable_rxdma_channel()
1225 			genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma3);  in e100_disable_rxdma_channel()
1229 		if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma5)) ==  in e100_disable_rxdma_channel()
1231 			genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma5);  in e100_disable_rxdma_channel()
1247 		genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma7);  in e100_enable_rxdma_channel()
1250 		genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma9);  in e100_enable_rxdma_channel()
1253 		genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma3);  in e100_enable_rxdma_channel()
1256 		genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma5);  in e100_enable_rxdma_channel()
1796 	if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) {  in receive_chars_dma()
2157 	if (data_read & IO_MASK(R_SERIAL0_READ, xoff_detect) ) {  in handle_ser_rx_interrupt_no_dma()
2162 	if (data_read & ( IO_MASK(R_SERIAL0_READ, framing_err) |  in handle_ser_rx_interrupt_no_dma()
2163 			  IO_MASK(R_SERIAL0_READ, par_err) |  in handle_ser_rx_interrupt_no_dma()
2164 			  IO_MASK(R_SERIAL0_READ, overrun) )) {  in handle_ser_rx_interrupt_no_dma()
2177 		if ( ((data_read & IO_MASK(R_SERIAL0_READ, data_in)) == 0) &&  in handle_ser_rx_interrupt_no_dma()
2178 		     (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) ) {  in handle_ser_rx_interrupt_no_dma()
2186 			if (data_read & IO_MASK(R_SERIAL0_READ, rxd)) {  in handle_ser_rx_interrupt_no_dma()
2214 				if (data_read & IO_MASK(R_SERIAL0_READ, par_err)) {  in handle_ser_rx_interrupt_no_dma()
2217 				} else if (data_read & IO_MASK(R_SERIAL0_READ, overrun)) {  in handle_ser_rx_interrupt_no_dma()
2220 				} else if (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) {  in handle_ser_rx_interrupt_no_dma()
2229 	} else if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) {  in handle_ser_rx_interrupt_no_dma()
2250 	if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) {  in handle_ser_rx_interrupt_no_dma()
2272 	if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) {  in handle_ser_rx_interrupt()
2510 		irq_mask1_rd &= (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) |  in ser_interrupt()
2511 				 IO_MASK(R_IRQ_MASK1_RD, ser1_ready) |  in ser_interrupt()
2512 				 IO_MASK(R_IRQ_MASK1_RD, ser2_ready) |  in ser_interrupt()
2513 				 IO_MASK(R_IRQ_MASK1_RD, ser3_ready));  in ser_interrupt()
2541 		ready_mask = irq_mask1_rd & (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) |  in ser_interrupt()
2542 					     IO_MASK(R_IRQ_MASK1_RD, ser1_ready) |  in ser_interrupt()
2543 					     IO_MASK(R_IRQ_MASK1_RD, ser2_ready) |  in ser_interrupt()
2544 					     IO_MASK(R_IRQ_MASK1_RD, ser3_ready));  in ser_interrupt()
2857 	info->rx_ctrl &= ~(IO_MASK(R_SERIAL0_REC_CTRL, rec_bitnr) |  in change_speed()
2858 			   IO_MASK(R_SERIAL0_REC_CTRL, rec_par_en) |  in change_speed()
2859 			   IO_MASK(R_SERIAL0_REC_CTRL, rec_par));  in change_speed()
2862 	info->tx_ctrl &= ~(IO_MASK(R_SERIAL0_TR_CTRL, tr_bitnr) |  in change_speed()
2863 			   IO_MASK(R_SERIAL0_TR_CTRL, tr_par_en) |  in change_speed()
2864 			   IO_MASK(R_SERIAL0_TR_CTRL, tr_par) |  in change_speed()
2865 			   IO_MASK(R_SERIAL0_TR_CTRL, stop_bits) |  in change_speed()
2866 			   IO_MASK(R_SERIAL0_TR_CTRL, auto_cts));  in change_speed()
4024 		if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect))  in seq_line_info()