441 	writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_tx_callback()
555 	writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_tx_refill()
591 		writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_tx_irq()
593 		writew(uap->im, uap->port.membase + UART011_IMSC);  in pl011_dma_tx_irq()
603 		writew(uap->im, uap->port.membase + UART011_IMSC);  in pl011_dma_tx_irq()
617 		writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_tx_stop()
643 				writew(uap->im, uap->port.membase +  in pl011_dma_tx_start()
649 			writew(uap->dmacr,  in pl011_dma_tx_start()
661 	writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_tx_start()
672 	writew(uap->port.x_char, uap->port.membase + UART01x_DR);  in pl011_dma_tx_start()
678 	writew(dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_tx_start()
706 		writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_flush_buffer()
746 	writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_rx_trigger_dma()
750 	writew(uap->im, uap->port.membase + UART011_IMSC);  in pl011_dma_rx_trigger_dma()
808 		writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS,  in pl011_dma_rx_chars()
857 	writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_rx_irq()
877 		writew(uap->im, uap->port.membase + UART011_IMSC);  in pl011_dma_rx_irq()
925 		writew(uap->im, uap->port.membase + UART011_IMSC);  in pl011_dma_rx_callback()
938 	writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_rx_stop()
982 		writew(uap->im, uap->port.membase + UART011_IMSC);  in pl011_dma_rx_poll()
1044 	writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_startup()
1052 		writew(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,  in pl011_dma_startup()
1083 	writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_shutdown()
1184 	writew(uap->im, uap->port.membase + UART011_IMSC);  in pl011_stop_tx()
1194 	writew(uap->im, uap->port.membase + UART011_IMSC);  in pl011_start_tx_pio()
1214 	writew(uap->im, uap->port.membase + UART011_IMSC);  in pl011_stop_rx()
1225 	writew(uap->im, uap->port.membase + UART011_IMSC);  in pl011_enable_ms()
1245 			writew(uap->im, uap->port.membase + UART011_IMSC);  in pl011_rx_chars()
1269 	writew(c, uap->port.membase + UART01x_DR);  in pl011_tx_char()
1344 	writew(0x00, uap->port.membase + UART011_ICR);  in check_apply_cts_event_workaround()
1370 			writew(status & ~(UART011_TXIS|UART011_RTIS|  in pl011_int()
1452 	writew(cr, uap->port.membase + UART011_CR);  in pl011_set_mctrl()
1468 	writew(lcr_h, uap->port.membase + uap->lcrh_tx);  in pl011_break_ctl()
1480 	writew(readw(regs + UART011_MIS), regs + UART011_ICR);  in pl011_quiesce_irqs()
1494 	writew(readw(regs + UART011_IMSC) & ~UART011_TXIM, regs + UART011_IMSC);  in pl011_quiesce_irqs()
1525 	writew(ch, uap->port.membase + UART01x_DR);  in pl011_put_poll_char()
1549 	writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS |  in pl011_hwinit()
1557 	writew(UART011_RTIM | UART011_RXIM, uap->port.membase + UART011_IMSC);  in pl011_hwinit()
1571 	writew(lcr_h, uap->port.membase + uap->lcrh_rx);  in pl011_write_lcr_h()
1579 			writew(0xff, uap->port.membase + UART011_MIS);  in pl011_write_lcr_h()
1580 		writew(lcr_h, uap->port.membase + uap->lcrh_tx);  in pl011_write_lcr_h()
1586 	writew(uap->im, uap->port.membase + UART011_IMSC);  in pl011_allocate_irq()
1601 	writew(UART011_RTIS | UART011_RXIS,  in pl011_enable_interrupts()
1606 	writew(uap->im, uap->port.membase + UART011_IMSC);  in pl011_enable_interrupts()
1625 	writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS);  in pl011_startup()
1632 	writew(cr, uap->port.membase + UART011_CR);  in pl011_startup()
1682       writew(val, uap->port.membase + lcrh);  in pl011_shutdown_channel()
1700 	writew(cr, uap->port.membase + UART011_CR);  in pl011_disable_uart()
1717 	writew(uap->im, uap->port.membase + UART011_IMSC);  in pl011_disable_interrupts()
1718 	writew(0xffff, uap->port.membase + UART011_ICR);  in pl011_disable_interrupts()
1871 	writew(0, port->membase + UART011_CR);  in pl011_set_termios()
1904 	writew(quot & 0x3f, port->membase + UART011_FBRD);  in pl011_set_termios()
1905 	writew(quot >> 6, port->membase + UART011_IBRD);  in pl011_set_termios()
1914 	writew(old_cr, port->membase + UART011_CR);  in pl011_set_termios()
2057 	writew(ch, uap->port.membase + UART01x_DR);  in pl011_console_putchar()
2085 		writew(new_cr, uap->port.membase + UART011_CR);  in pl011_console_write()
2098 		writew(old_cr, uap->port.membase + UART011_CR);  in pl011_console_write()
2337 	writew(0, uap->port.membase + UART011_IMSC);  in pl011_register_port()
2338 	writew(0xffff, uap->port.membase + UART011_ICR);  in pl011_register_port()