199 		status = readw(uap->port.membase + UART01x_FR);  in pl011_fifo_to_tty()
204 		ch = readw(uap->port.membase + UART01x_DR) |  in pl011_fifo_to_tty()
663 	if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) {  in pl011_dma_tx_start()
1078 	while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)  in pl011_dma_shutdown()
1266 	    readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)  in pl011_tx_char()
1316 	status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;  in pl011_modem_status()
1351 	dummy_read = readw(uap->port.membase + UART011_ICR);  in check_apply_cts_event_workaround()
1352 	dummy_read = readw(uap->port.membase + UART011_ICR);  in check_apply_cts_event_workaround()
1364 	imsc = readw(uap->port.membase + UART011_IMSC);  in pl011_int()
1365 	status = readw(uap->port.membase + UART011_RIS) & imsc;  in pl011_int()
1389 			status = readw(uap->port.membase + UART011_RIS) & imsc;  in pl011_int()
1403 	unsigned int status = readw(uap->port.membase + UART01x_FR);  in pl011_tx_empty()
1412 	unsigned int status = readw(uap->port.membase + UART01x_FR);  in pl011_get_mctrl()
1432 	cr = readw(uap->port.membase + UART011_CR);  in pl011_set_mctrl()
1463 	lcr_h = readw(uap->port.membase + uap->lcrh_tx);  in pl011_break_ctl()
1480 	writew(readw(regs + UART011_MIS), regs + UART011_ICR);  in pl011_quiesce_irqs()
1494 	writew(readw(regs + UART011_IMSC) & ~UART011_TXIM, regs + UART011_IMSC);  in pl011_quiesce_irqs()
1509 	status = readw(uap->port.membase + UART01x_FR);  in pl011_get_poll_char()
1513 	return readw(uap->port.membase + UART01x_DR);  in pl011_get_poll_char()
1522 	while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)  in pl011_put_poll_char()
1556 	uap->im = readw(uap->port.membase + UART011_IMSC);  in pl011_hwinit()
1639 	uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;  in pl011_startup()
1680       val = readw(uap->port.membase + lcrh);  in pl011_shutdown_channel()
1696 	cr = readw(uap->port.membase + UART011_CR);  in pl011_disable_uart()
1870 	old_cr = readw(port->membase + UART011_CR);  in pl011_set_termios()
2055 	while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)  in pl011_console_putchar()
2082 		old_cr = readw(uap->port.membase + UART011_CR);  in pl011_console_write()
2095 		status = readw(uap->port.membase + UART01x_FR);  in pl011_console_write()
2111 	if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) {  in pl011_console_get_options()
2114 		lcr_h = readw(uap->port.membase + uap->lcrh_tx);  in pl011_console_get_options()
2129 		ibrd = readw(uap->port.membase + UART011_IBRD);  in pl011_console_get_options()
2130 		fbrd = readw(uap->port.membase + UART011_FBRD);  in pl011_console_get_options()
2135 			if (readw(uap->port.membase + UART011_CR)  in pl011_console_get_options()