Lines Matching refs:port
164 struct uart_port port; member
199 status = readw(uap->port.membase + UART01x_FR); in pl011_fifo_to_tty()
204 ch = readw(uap->port.membase + UART01x_DR) | in pl011_fifo_to_tty()
207 uap->port.icount.rx++; in pl011_fifo_to_tty()
213 uap->port.icount.brk++; in pl011_fifo_to_tty()
214 if (uart_handle_break(&uap->port)) in pl011_fifo_to_tty()
217 uap->port.icount.parity++; in pl011_fifo_to_tty()
219 uap->port.icount.frame++; in pl011_fifo_to_tty()
221 uap->port.icount.overrun++; in pl011_fifo_to_tty()
223 ch &= uap->port.read_status_mask; in pl011_fifo_to_tty()
233 if (uart_handle_sysrq_char(&uap->port, ch & 255)) in pl011_fifo_to_tty()
236 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); in pl011_fifo_to_tty()
284 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev); in pl011_dma_probe()
285 struct device *dev = uap->port.dev; in pl011_dma_probe()
287 .dst_addr = uap->port.mapbase + UART01x_DR, in pl011_dma_probe()
306 dev_info(uap->port.dev, "no DMA platform data\n"); in pl011_dma_probe()
317 dev_err(uap->port.dev, "no TX DMA channel!\n"); in pl011_dma_probe()
325 dev_info(uap->port.dev, "DMA channel TX %s\n", in pl011_dma_probe()
335 dev_err(uap->port.dev, "no RX DMA channel!\n"); in pl011_dma_probe()
342 .src_addr = uap->port.mapbase + UART01x_DR, in pl011_dma_probe()
359 dev_info(uap->port.dev, in pl011_dma_probe()
406 dev_info(uap->port.dev, "DMA channel RX %s\n", in pl011_dma_probe()
434 spin_lock_irqsave(&uap->port.lock, flags); in pl011_dma_tx_callback()
441 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_tx_callback()
452 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) || in pl011_dma_tx_callback()
453 uart_circ_empty(&uap->port.state->xmit)) { in pl011_dma_tx_callback()
455 spin_unlock_irqrestore(&uap->port.lock, flags); in pl011_dma_tx_callback()
466 spin_unlock_irqrestore(&uap->port.lock, flags); in pl011_dma_tx_callback()
483 struct circ_buf *xmit = &uap->port.state->xmit; in pl011_dma_tx_refill()
527 dev_dbg(uap->port.dev, "unable to map TX DMA\n"); in pl011_dma_tx_refill()
540 dev_dbg(uap->port.dev, "TX DMA busy\n"); in pl011_dma_tx_refill()
555 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_tx_refill()
563 uap->port.icount.tx += count; in pl011_dma_tx_refill()
566 uart_write_wakeup(&uap->port); in pl011_dma_tx_refill()
591 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_tx_irq()
593 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_dma_tx_irq()
603 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_dma_tx_irq()
617 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_tx_stop()
636 if (!uap->port.x_char) { in pl011_dma_tx_start()
643 writew(uap->im, uap->port.membase + in pl011_dma_tx_start()
650 uap->port.membase + UART011_DMACR); in pl011_dma_tx_start()
661 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_tx_start()
663 if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) { in pl011_dma_tx_start()
672 writew(uap->port.x_char, uap->port.membase + UART01x_DR); in pl011_dma_tx_start()
673 uap->port.icount.tx++; in pl011_dma_tx_start()
674 uap->port.x_char = 0; in pl011_dma_tx_start()
678 writew(dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_tx_start()
687 static void pl011_dma_flush_buffer(struct uart_port *port) in pl011_dma_flush_buffer() argument
688 __releases(&uap->port.lock) in pl011_dma_flush_buffer()
689 __acquires(&uap->port.lock) in pl011_dma_flush_buffer()
692 container_of(port, struct uart_amba_port, port); in pl011_dma_flush_buffer()
698 spin_unlock(&uap->port.lock); in pl011_dma_flush_buffer()
700 spin_lock(&uap->port.lock); in pl011_dma_flush_buffer()
706 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_flush_buffer()
746 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_rx_trigger_dma()
750 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_dma_rx_trigger_dma()
764 struct tty_port *port = &uap->port.state->port; in pl011_dma_rx_chars() local
789 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, in pl011_dma_rx_chars()
792 uap->port.icount.rx += dma_count; in pl011_dma_rx_chars()
794 dev_warn(uap->port.dev, in pl011_dma_rx_chars()
809 uap->port.membase + UART011_ICR); in pl011_dma_rx_chars()
825 spin_unlock(&uap->port.lock); in pl011_dma_rx_chars()
826 dev_vdbg(uap->port.dev, in pl011_dma_rx_chars()
829 tty_flip_buffer_push(port); in pl011_dma_rx_chars()
830 spin_lock(&uap->port.lock); in pl011_dma_rx_chars()
849 dev_err(uap->port.dev, "unable to pause DMA transfer\n"); in pl011_dma_rx_irq()
853 dev_err(uap->port.dev, "unable to pause DMA transfer\n"); in pl011_dma_rx_irq()
857 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_rx_irq()
874 dev_dbg(uap->port.dev, "could not retrigger RX DMA job " in pl011_dma_rx_irq()
877 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_dma_rx_irq()
900 spin_lock_irq(&uap->port.lock); in pl011_dma_rx_callback()
916 spin_unlock_irq(&uap->port.lock); in pl011_dma_rx_callback()
922 dev_dbg(uap->port.dev, "could not retrigger RX DMA job " in pl011_dma_rx_callback()
925 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_dma_rx_callback()
938 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_rx_stop()
949 struct tty_port *port = &uap->port.state->port; in pl011_dma_rx_poll() local
964 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, in pl011_dma_rx_poll()
970 tty_flip_buffer_push(port); in pl011_dma_rx_poll()
979 spin_lock_irqsave(&uap->port.lock, flags); in pl011_dma_rx_poll()
982 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_dma_rx_poll()
983 spin_unlock_irqrestore(&uap->port.lock, flags); in pl011_dma_rx_poll()
1006 dev_err(uap->port.dev, "no memory for DMA TX buffer\n"); in pl011_dma_startup()
1007 uap->port.fifosize = uap->fifosize; in pl011_dma_startup()
1014 uap->port.fifosize = PL011_DMA_BUFFER_SIZE; in pl011_dma_startup()
1024 dev_err(uap->port.dev, "failed to init DMA %s: %d\n", in pl011_dma_startup()
1032 dev_err(uap->port.dev, "failed to init DMA %s: %d\n", in pl011_dma_startup()
1044 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_startup()
1053 uap->port.membase + ST_UART011_DMAWM); in pl011_dma_startup()
1057 dev_dbg(uap->port.dev, "could not trigger initial " in pl011_dma_startup()
1078 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY) in pl011_dma_shutdown()
1081 spin_lock_irq(&uap->port.lock); in pl011_dma_shutdown()
1083 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_shutdown()
1084 spin_unlock_irq(&uap->port.lock); in pl011_dma_shutdown()
1178 static void pl011_stop_tx(struct uart_port *port) in pl011_stop_tx() argument
1181 container_of(port, struct uart_amba_port, port); in pl011_stop_tx()
1184 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_stop_tx()
1194 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_start_tx_pio()
1198 static void pl011_start_tx(struct uart_port *port) in pl011_start_tx() argument
1201 container_of(port, struct uart_amba_port, port); in pl011_start_tx()
1207 static void pl011_stop_rx(struct uart_port *port) in pl011_stop_rx() argument
1210 container_of(port, struct uart_amba_port, port); in pl011_stop_rx()
1214 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_stop_rx()
1219 static void pl011_enable_ms(struct uart_port *port) in pl011_enable_ms() argument
1222 container_of(port, struct uart_amba_port, port); in pl011_enable_ms()
1225 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_enable_ms()
1229 __releases(&uap->port.lock) in pl011_rx_chars()
1230 __acquires(&uap->port.lock) in pl011_rx_chars()
1234 spin_unlock(&uap->port.lock); in pl011_rx_chars()
1235 tty_flip_buffer_push(&uap->port.state->port); in pl011_rx_chars()
1242 dev_dbg(uap->port.dev, "could not trigger RX DMA job " in pl011_rx_chars()
1245 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_rx_chars()
1259 spin_lock(&uap->port.lock); in pl011_rx_chars()
1266 readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) in pl011_tx_char()
1269 writew(c, uap->port.membase + UART01x_DR); in pl011_tx_char()
1270 uap->port.icount.tx++; in pl011_tx_char()
1277 struct circ_buf *xmit = &uap->port.state->xmit; in pl011_tx_chars()
1280 if (uap->port.x_char) { in pl011_tx_chars()
1281 if (!pl011_tx_char(uap, uap->port.x_char, from_irq)) in pl011_tx_chars()
1283 uap->port.x_char = 0; in pl011_tx_chars()
1286 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { in pl011_tx_chars()
1287 pl011_stop_tx(&uap->port); in pl011_tx_chars()
1306 uart_write_wakeup(&uap->port); in pl011_tx_chars()
1309 pl011_stop_tx(&uap->port); in pl011_tx_chars()
1316 status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; in pl011_modem_status()
1325 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); in pl011_modem_status()
1328 uap->port.icount.dsr++; in pl011_modem_status()
1331 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS); in pl011_modem_status()
1333 wake_up_interruptible(&uap->port.state->port.delta_msr_wait); in pl011_modem_status()
1344 writew(0x00, uap->port.membase + UART011_ICR); in check_apply_cts_event_workaround()
1351 dummy_read = readw(uap->port.membase + UART011_ICR); in check_apply_cts_event_workaround()
1352 dummy_read = readw(uap->port.membase + UART011_ICR); in check_apply_cts_event_workaround()
1363 spin_lock_irqsave(&uap->port.lock, flags); in pl011_int()
1364 imsc = readw(uap->port.membase + UART011_IMSC); in pl011_int()
1365 status = readw(uap->port.membase + UART011_RIS) & imsc; in pl011_int()
1372 uap->port.membase + UART011_ICR); in pl011_int()
1389 status = readw(uap->port.membase + UART011_RIS) & imsc; in pl011_int()
1394 spin_unlock_irqrestore(&uap->port.lock, flags); in pl011_int()
1399 static unsigned int pl011_tx_empty(struct uart_port *port) in pl011_tx_empty() argument
1402 container_of(port, struct uart_amba_port, port); in pl011_tx_empty()
1403 unsigned int status = readw(uap->port.membase + UART01x_FR); in pl011_tx_empty()
1407 static unsigned int pl011_get_mctrl(struct uart_port *port) in pl011_get_mctrl() argument
1410 container_of(port, struct uart_amba_port, port); in pl011_get_mctrl()
1412 unsigned int status = readw(uap->port.membase + UART01x_FR); in pl011_get_mctrl()
1426 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl) in pl011_set_mctrl() argument
1429 container_of(port, struct uart_amba_port, port); in pl011_set_mctrl()
1432 cr = readw(uap->port.membase + UART011_CR); in pl011_set_mctrl()
1452 writew(cr, uap->port.membase + UART011_CR); in pl011_set_mctrl()
1455 static void pl011_break_ctl(struct uart_port *port, int break_state) in pl011_break_ctl() argument
1458 container_of(port, struct uart_amba_port, port); in pl011_break_ctl()
1462 spin_lock_irqsave(&uap->port.lock, flags); in pl011_break_ctl()
1463 lcr_h = readw(uap->port.membase + uap->lcrh_tx); in pl011_break_ctl()
1468 writew(lcr_h, uap->port.membase + uap->lcrh_tx); in pl011_break_ctl()
1469 spin_unlock_irqrestore(&uap->port.lock, flags); in pl011_break_ctl()
1474 static void pl011_quiesce_irqs(struct uart_port *port) in pl011_quiesce_irqs() argument
1477 container_of(port, struct uart_amba_port, port); in pl011_quiesce_irqs()
1478 unsigned char __iomem *regs = uap->port.membase; in pl011_quiesce_irqs()
1497 static int pl011_get_poll_char(struct uart_port *port) in pl011_get_poll_char() argument
1500 container_of(port, struct uart_amba_port, port); in pl011_get_poll_char()
1507 pl011_quiesce_irqs(port); in pl011_get_poll_char()
1509 status = readw(uap->port.membase + UART01x_FR); in pl011_get_poll_char()
1513 return readw(uap->port.membase + UART01x_DR); in pl011_get_poll_char()
1516 static void pl011_put_poll_char(struct uart_port *port, in pl011_put_poll_char() argument
1520 container_of(port, struct uart_amba_port, port); in pl011_put_poll_char()
1522 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) in pl011_put_poll_char()
1525 writew(ch, uap->port.membase + UART01x_DR); in pl011_put_poll_char()
1530 static int pl011_hwinit(struct uart_port *port) in pl011_hwinit() argument
1533 container_of(port, struct uart_amba_port, port); in pl011_hwinit()
1537 pinctrl_pm_select_default_state(port->dev); in pl011_hwinit()
1546 uap->port.uartclk = clk_get_rate(uap->clk); in pl011_hwinit()
1550 UART011_RTIS | UART011_RXIS, uap->port.membase + UART011_ICR); in pl011_hwinit()
1556 uap->im = readw(uap->port.membase + UART011_IMSC); in pl011_hwinit()
1557 writew(UART011_RTIM | UART011_RXIM, uap->port.membase + UART011_IMSC); in pl011_hwinit()
1559 if (dev_get_platdata(uap->port.dev)) { in pl011_hwinit()
1562 plat = dev_get_platdata(uap->port.dev); in pl011_hwinit()
1571 writew(lcr_h, uap->port.membase + uap->lcrh_rx); in pl011_write_lcr_h()
1579 writew(0xff, uap->port.membase + UART011_MIS); in pl011_write_lcr_h()
1580 writew(lcr_h, uap->port.membase + uap->lcrh_tx); in pl011_write_lcr_h()
1586 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_allocate_irq()
1588 return request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap); in pl011_allocate_irq()
1598 spin_lock_irq(&uap->port.lock); in pl011_enable_interrupts()
1602 uap->port.membase + UART011_ICR); in pl011_enable_interrupts()
1606 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_enable_interrupts()
1607 spin_unlock_irq(&uap->port.lock); in pl011_enable_interrupts()
1610 static int pl011_startup(struct uart_port *port) in pl011_startup() argument
1613 container_of(port, struct uart_amba_port, port); in pl011_startup()
1617 retval = pl011_hwinit(port); in pl011_startup()
1625 writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS); in pl011_startup()
1627 spin_lock_irq(&uap->port.lock); in pl011_startup()
1632 writew(cr, uap->port.membase + UART011_CR); in pl011_startup()
1634 spin_unlock_irq(&uap->port.lock); in pl011_startup()
1639 uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; in pl011_startup()
1653 static int sbsa_uart_startup(struct uart_port *port) in sbsa_uart_startup() argument
1656 container_of(port, struct uart_amba_port, port); in sbsa_uart_startup()
1659 retval = pl011_hwinit(port); in sbsa_uart_startup()
1680 val = readw(uap->port.membase + lcrh); in pl011_shutdown_channel()
1682 writew(val, uap->port.membase + lcrh); in pl011_shutdown_channel()
1695 spin_lock_irq(&uap->port.lock); in pl011_disable_uart()
1696 cr = readw(uap->port.membase + UART011_CR); in pl011_disable_uart()
1700 writew(cr, uap->port.membase + UART011_CR); in pl011_disable_uart()
1701 spin_unlock_irq(&uap->port.lock); in pl011_disable_uart()
1713 spin_lock_irq(&uap->port.lock); in pl011_disable_interrupts()
1717 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_disable_interrupts()
1718 writew(0xffff, uap->port.membase + UART011_ICR); in pl011_disable_interrupts()
1720 spin_unlock_irq(&uap->port.lock); in pl011_disable_interrupts()
1723 static void pl011_shutdown(struct uart_port *port) in pl011_shutdown() argument
1726 container_of(port, struct uart_amba_port, port); in pl011_shutdown()
1732 free_irq(uap->port.irq, uap); in pl011_shutdown()
1741 pinctrl_pm_select_sleep_state(port->dev); in pl011_shutdown()
1743 if (dev_get_platdata(uap->port.dev)) { in pl011_shutdown()
1746 plat = dev_get_platdata(uap->port.dev); in pl011_shutdown()
1751 if (uap->port.ops->flush_buffer) in pl011_shutdown()
1752 uap->port.ops->flush_buffer(port); in pl011_shutdown()
1755 static void sbsa_uart_shutdown(struct uart_port *port) in sbsa_uart_shutdown() argument
1758 container_of(port, struct uart_amba_port, port); in sbsa_uart_shutdown()
1762 free_irq(uap->port.irq, uap); in sbsa_uart_shutdown()
1764 if (uap->port.ops->flush_buffer) in sbsa_uart_shutdown()
1765 uap->port.ops->flush_buffer(port); in sbsa_uart_shutdown()
1769 pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios) in pl011_setup_status_masks() argument
1771 port->read_status_mask = UART011_DR_OE | 255; in pl011_setup_status_masks()
1773 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE; in pl011_setup_status_masks()
1775 port->read_status_mask |= UART011_DR_BE; in pl011_setup_status_masks()
1780 port->ignore_status_mask = 0; in pl011_setup_status_masks()
1782 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE; in pl011_setup_status_masks()
1784 port->ignore_status_mask |= UART011_DR_BE; in pl011_setup_status_masks()
1790 port->ignore_status_mask |= UART011_DR_OE; in pl011_setup_status_masks()
1797 port->ignore_status_mask |= UART_DUMMY_DR_RX; in pl011_setup_status_masks()
1801 pl011_set_termios(struct uart_port *port, struct ktermios *termios, in pl011_set_termios() argument
1805 container_of(port, struct uart_amba_port, port); in pl011_set_termios()
1818 baud = uart_get_baud_rate(port, termios, old, 0, in pl011_set_termios()
1819 port->uartclk / clkdiv); in pl011_set_termios()
1828 if (baud > port->uartclk/16) in pl011_set_termios()
1829 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud); in pl011_set_termios()
1831 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud); in pl011_set_termios()
1857 spin_lock_irqsave(&port->lock, flags); in pl011_set_termios()
1862 uart_update_timeout(port, termios->c_cflag, baud); in pl011_set_termios()
1864 pl011_setup_status_masks(port, termios); in pl011_set_termios()
1866 if (UART_ENABLE_MS(port, termios->c_cflag)) in pl011_set_termios()
1867 pl011_enable_ms(port); in pl011_set_termios()
1870 old_cr = readw(port->membase + UART011_CR); in pl011_set_termios()
1871 writew(0, port->membase + UART011_CR); in pl011_set_termios()
1885 if (baud > port->uartclk / 16) in pl011_set_termios()
1904 writew(quot & 0x3f, port->membase + UART011_FBRD); in pl011_set_termios()
1905 writew(quot >> 6, port->membase + UART011_IBRD); in pl011_set_termios()
1914 writew(old_cr, port->membase + UART011_CR); in pl011_set_termios()
1916 spin_unlock_irqrestore(&port->lock, flags); in pl011_set_termios()
1920 sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios, in sbsa_uart_set_termios() argument
1924 container_of(port, struct uart_amba_port, port); in sbsa_uart_set_termios()
1934 spin_lock_irqsave(&port->lock, flags); in sbsa_uart_set_termios()
1935 uart_update_timeout(port, CS8, uap->fixed_baud); in sbsa_uart_set_termios()
1936 pl011_setup_status_masks(port, termios); in sbsa_uart_set_termios()
1937 spin_unlock_irqrestore(&port->lock, flags); in sbsa_uart_set_termios()
1940 static const char *pl011_type(struct uart_port *port) in pl011_type() argument
1943 container_of(port, struct uart_amba_port, port); in pl011_type()
1944 return uap->port.type == PORT_AMBA ? uap->type : NULL; in pl011_type()
1950 static void pl011_release_port(struct uart_port *port) in pl011_release_port() argument
1952 release_mem_region(port->mapbase, SZ_4K); in pl011_release_port()
1958 static int pl011_request_port(struct uart_port *port) in pl011_request_port() argument
1960 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011") in pl011_request_port()
1967 static void pl011_config_port(struct uart_port *port, int flags) in pl011_config_port() argument
1970 port->type = PORT_AMBA; in pl011_config_port()
1971 pl011_request_port(port); in pl011_config_port()
1978 static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser) in pl011_verify_port() argument
2015 static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) in sbsa_uart_set_mctrl() argument
2019 static unsigned int sbsa_uart_get_mctrl(struct uart_port *port) in sbsa_uart_get_mctrl() argument
2050 static void pl011_console_putchar(struct uart_port *port, int ch) in pl011_console_putchar() argument
2053 container_of(port, struct uart_amba_port, port); in pl011_console_putchar()
2055 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) in pl011_console_putchar()
2057 writew(ch, uap->port.membase + UART01x_DR); in pl011_console_putchar()
2071 if (uap->port.sysrq) in pl011_console_write()
2074 locked = spin_trylock(&uap->port.lock); in pl011_console_write()
2076 spin_lock(&uap->port.lock); in pl011_console_write()
2082 old_cr = readw(uap->port.membase + UART011_CR); in pl011_console_write()
2085 writew(new_cr, uap->port.membase + UART011_CR); in pl011_console_write()
2088 uart_console_write(&uap->port, s, count, pl011_console_putchar); in pl011_console_write()
2095 status = readw(uap->port.membase + UART01x_FR); in pl011_console_write()
2098 writew(old_cr, uap->port.membase + UART011_CR); in pl011_console_write()
2101 spin_unlock(&uap->port.lock); in pl011_console_write()
2111 if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) { in pl011_console_get_options()
2114 lcr_h = readw(uap->port.membase + uap->lcrh_tx); in pl011_console_get_options()
2129 ibrd = readw(uap->port.membase + UART011_IBRD); in pl011_console_get_options()
2130 fbrd = readw(uap->port.membase + UART011_FBRD); in pl011_console_get_options()
2132 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); in pl011_console_get_options()
2135 if (readw(uap->port.membase + UART011_CR) in pl011_console_get_options()
2163 pinctrl_pm_select_default_state(uap->port.dev); in pl011_console_setup()
2169 if (dev_get_platdata(uap->port.dev)) { in pl011_console_setup()
2172 plat = dev_get_platdata(uap->port.dev); in pl011_console_setup()
2177 uap->port.uartclk = clk_get_rate(uap->clk); in pl011_console_setup()
2189 return uart_set_options(&uap->port, co, baud, parity, bits, flow); in pl011_console_setup()
2205 static void pl011_putc(struct uart_port *port, int c) in pl011_putc() argument
2207 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) in pl011_putc()
2209 writeb(c, port->membase + UART01x_DR); in pl011_putc()
2210 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY) in pl011_putc()
2218 uart_console_write(&dev->port, s, n, pl011_putc); in pl011_early_write()
2224 if (!device->port.membase) in pl011_early_console_setup()
2319 uap->port.dev = dev; in pl011_setup_port()
2320 uap->port.mapbase = mmiobase->start; in pl011_setup_port()
2321 uap->port.membase = base; in pl011_setup_port()
2322 uap->port.iotype = UPIO_MEM; in pl011_setup_port()
2323 uap->port.fifosize = uap->fifosize; in pl011_setup_port()
2324 uap->port.flags = UPF_BOOT_AUTOCONF; in pl011_setup_port()
2325 uap->port.line = index; in pl011_setup_port()
2337 writew(0, uap->port.membase + UART011_IMSC); in pl011_register_port()
2338 writew(0xffff, uap->port.membase + UART011_ICR); in pl011_register_port()
2343 dev_err(uap->port.dev, in pl011_register_port()
2349 ret = uart_add_one_port(&amba_reg, &uap->port); in pl011_register_port()
2379 uap->port.irq = dev->irq[0]; in pl011_probe()
2380 uap->port.ops = &amba_pl011_pops; in pl011_probe()
2397 uart_remove_one_port(&amba_reg, &uap->port); in pl011_remove()
2410 return uart_suspend_port(&amba_reg, &uap->port); in pl011_suspend()
2420 return uart_resume_port(&amba_reg, &uap->port); in pl011_resume()
2458 uap->port.irq = platform_get_irq(pdev, 0); in sbsa_uart_probe()
2459 uap->port.ops = &sbsa_uart_pops; in sbsa_uart_probe()
2479 uart_remove_one_port(&amba_reg, &uap->port); in sbsa_uart_remove()