167 	unsigned int		dmacr;		/* dma control reg */  member
432 	u16 dmacr;  in pl011_dma_tx_callback()  local
439 	dmacr = uap->dmacr;  in pl011_dma_tx_callback()
440 	uap->dmacr = dmacr & ~UART011_TXDMAE;  in pl011_dma_tx_callback()
441 	writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_tx_callback()
452 	if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||  in pl011_dma_tx_callback()
554 	uap->dmacr |= UART011_TXDMAE;  in pl011_dma_tx_refill()
555 	writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_tx_refill()
590 		uap->dmacr |= UART011_TXDMAE;  in pl011_dma_tx_irq()
591 		writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_tx_irq()
616 		uap->dmacr &= ~UART011_TXDMAE;  in pl011_dma_tx_stop()
617 		writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_tx_stop()
631 	u16 dmacr;  in pl011_dma_tx_start()  local
647 		} else if (!(uap->dmacr & UART011_TXDMAE)) {  in pl011_dma_tx_start()
648 			uap->dmacr |= UART011_TXDMAE;  in pl011_dma_tx_start()
649 			writew(uap->dmacr,  in pl011_dma_tx_start()
659 	dmacr = uap->dmacr;  in pl011_dma_tx_start()
660 	uap->dmacr &= ~UART011_TXDMAE;  in pl011_dma_tx_start()
661 	writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_tx_start()
677 	uap->dmacr = dmacr;  in pl011_dma_tx_start()
678 	writew(dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_tx_start()
705 		uap->dmacr &= ~UART011_TXDMAE;  in pl011_dma_flush_buffer()
706 		writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_flush_buffer()
745 	uap->dmacr |= UART011_RXDMAE;  in pl011_dma_rx_trigger_dma()
746 	writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_rx_trigger_dma()
856 	uap->dmacr &= ~UART011_RXDMAE;  in pl011_dma_rx_irq()
857 	writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_rx_irq()
937 	uap->dmacr &= ~UART011_RXDMAE;  in pl011_dma_rx_stop()
938 	writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_rx_stop()
1043 	uap->dmacr |= UART011_DMAONERR;  in pl011_dma_startup()
1044 	writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_startup()
1082 	uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);  in pl011_dma_shutdown()
1083 	writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_shutdown()