Lines Matching refs:ChP
381 #define sClrBreak(ChP) \ argument
383 (ChP)->TxControl[3] &= ~SETBREAK; \
384 out32((ChP)->IndexAddr,(ChP)->TxControl); \
393 #define sClrDTR(ChP) \ argument
395 (ChP)->TxControl[3] &= ~SET_DTR; \
396 out32((ChP)->IndexAddr,(ChP)->TxControl); \
405 #define sClrRTS(ChP) \ argument
407 if ((ChP)->rtsToggle) break; \
408 (ChP)->TxControl[3] &= ~SET_RTS; \
409 out32((ChP)->IndexAddr,(ChP)->TxControl); \
418 #define sClrTxXOFF(ChP) \ argument
420 sOutB((ChP)->Cmd,TXOVERIDE | (Byte_t)(ChP)->ChanNum); \
421 sOutB((ChP)->Cmd,(Byte_t)(ChP)->ChanNum); \
480 #define sDisCTSFlowCtl(ChP) \ argument
482 (ChP)->TxControl[2] &= ~CTSFC_EN; \
483 out32((ChP)->IndexAddr,(ChP)->TxControl); \
492 #define sDisIXANY(ChP) \ argument
494 (ChP)->R[0x0e] = 0x86; \
495 out32((ChP)->IndexAddr,&(ChP)->R[0x0c]); \
506 #define sDisParity(ChP) \ argument
508 (ChP)->TxControl[2] &= ~PARITY_EN; \
509 out32((ChP)->IndexAddr,(ChP)->TxControl); \
518 #define sDisRTSToggle(ChP) \ argument
520 (ChP)->TxControl[2] &= ~RTSTOG_EN; \
521 out32((ChP)->IndexAddr,(ChP)->TxControl); \
522 (ChP)->rtsToggle = 0; \
531 #define sDisRxFIFO(ChP) \ argument
533 (ChP)->R[0x32] = 0x0a; \
534 out32((ChP)->IndexAddr,&(ChP)->R[0x30]); \
546 #define sDisRxStatusMode(ChP) sOutW((ChP)->ChanStat,0) argument
558 #define sDisTransmit(ChP) \ argument
560 (ChP)->TxControl[3] &= ~TX_ENABLE; \
561 out32((ChP)->IndexAddr,(ChP)->TxControl); \
570 #define sDisTxSoftFlowCtl(ChP) \ argument
572 (ChP)->R[0x06] = 0x8a; \
573 out32((ChP)->IndexAddr,&(ChP)->R[0x04]); \
595 #define sEnCTSFlowCtl(ChP) \ argument
597 (ChP)->TxControl[2] |= CTSFC_EN; \
598 out32((ChP)->IndexAddr,(ChP)->TxControl); \
607 #define sEnIXANY(ChP) \ argument
609 (ChP)->R[0x0e] = 0x21; \
610 out32((ChP)->IndexAddr,&(ChP)->R[0x0c]); \
624 #define sEnParity(ChP) \ argument
626 (ChP)->TxControl[2] |= PARITY_EN; \
627 out32((ChP)->IndexAddr,(ChP)->TxControl); \
638 #define sEnRTSToggle(ChP) \ argument
640 (ChP)->RxControl[2] &= ~RTSFC_EN; \
641 out32((ChP)->IndexAddr,(ChP)->RxControl); \
642 (ChP)->TxControl[2] |= RTSTOG_EN; \
643 (ChP)->TxControl[3] &= ~SET_RTS; \
644 out32((ChP)->IndexAddr,(ChP)->TxControl); \
645 (ChP)->rtsToggle = 1; \
654 #define sEnRxFIFO(ChP) \ argument
656 (ChP)->R[0x32] = 0x08; \
657 out32((ChP)->IndexAddr,&(ChP)->R[0x30]); \
675 #define sEnRxProcessor(ChP) \ argument
677 (ChP)->RxControl[2] |= RXPROC_EN; \
678 out32((ChP)->IndexAddr,(ChP)->RxControl); \
691 #define sEnRxStatusMode(ChP) sOutW((ChP)->ChanStat,STATMODE) argument
699 #define sEnTransmit(ChP) \ argument
701 (ChP)->TxControl[3] |= TX_ENABLE; \
702 out32((ChP)->IndexAddr,(ChP)->TxControl); \
711 #define sEnTxSoftFlowCtl(ChP) \ argument
713 (ChP)->R[0x06] = 0xc5; \
714 out32((ChP)->IndexAddr,&(ChP)->R[0x04]); \
753 #define sGetChanIntID(ChP) (sInB((ChP)->IntID) & (RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA… argument
763 #define sGetChanNum(ChP) (ChP)->ChanNum argument
791 #define sGetChanStatus(ChP) sInW((ChP)->ChanStat) argument
807 #define sGetChanStatusLo(ChP) sInB((ByteIO_t)(ChP)->ChanStat) argument
814 #define sGetChanRI(ChP) ((ChP)->CtlP->AltChanRingIndicator ? \
815 (sInB((ByteIO_t)((ChP)->ChanStat+8)) & DSR_ACT) : \
816 (((ChP)->CtlP->boardType == ROCKET_TYPE_PC104) ? \
817 (!(sInB((ChP)->CtlP->AiopIO[3]) & sBitMapSetTbl[(ChP)->ChanNum])) : \
860 #define sGetRxCnt(ChP) sInW((ChP)->TxRxCount) argument
871 #define sGetTxCnt(ChP) sInB((ByteIO_t)(ChP)->TxRxCount) argument
880 #define sGetTxRxDataIO(ChP) (ChP)->TxRxData argument
891 #define sInitChanDefaults(ChP) \ argument
893 (ChP)->CtlP = NULLCTLPTR; \
894 (ChP)->AiopNum = NULLAIOP; \
895 (ChP)->ChanID = AIOPID_NULL; \
896 (ChP)->ChanNum = NULLCHAN; \
918 #define sSendBreak(ChP) \ argument
920 (ChP)->TxControl[3] |= SETBREAK; \
921 out32((ChP)->IndexAddr,(ChP)->TxControl); \
931 #define sSetBaud(ChP,DIVISOR) \ argument
933 (ChP)->BaudDiv[2] = (Byte_t)(DIVISOR); \
934 (ChP)->BaudDiv[3] = (Byte_t)((DIVISOR) >> 8); \
935 out32((ChP)->IndexAddr,(ChP)->BaudDiv); \
944 #define sSetData7(ChP) \ argument
946 (ChP)->TxControl[2] &= ~DATA8BIT; \
947 out32((ChP)->IndexAddr,(ChP)->TxControl); \
956 #define sSetData8(ChP) \ argument
958 (ChP)->TxControl[2] |= DATA8BIT; \
959 out32((ChP)->IndexAddr,(ChP)->TxControl); \
968 #define sSetDTR(ChP) \ argument
970 (ChP)->TxControl[3] |= SET_DTR; \
971 out32((ChP)->IndexAddr,(ChP)->TxControl); \
985 #define sSetEvenParity(ChP) \ argument
987 (ChP)->TxControl[2] |= EVEN_PAR; \
988 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1002 #define sSetOddParity(ChP) \ argument
1004 (ChP)->TxControl[2] &= ~EVEN_PAR; \
1005 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1014 #define sSetRTS(ChP) \ argument
1016 if ((ChP)->rtsToggle) break; \
1017 (ChP)->TxControl[3] |= SET_RTS; \
1018 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1040 #define sSetRxTrigger(ChP,LEVEL) \ argument
1042 (ChP)->RxControl[2] &= ~TRIG_MASK; \
1043 (ChP)->RxControl[2] |= LEVEL; \
1044 out32((ChP)->IndexAddr,(ChP)->RxControl); \
1053 #define sSetStop1(ChP) \ argument
1055 (ChP)->TxControl[2] &= ~STOP2; \
1056 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1065 #define sSetStop2(ChP) \ argument
1067 (ChP)->TxControl[2] |= STOP2; \
1068 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1078 #define sSetTxXOFFChar(ChP,CH) \ argument
1080 (ChP)->R[0x07] = (CH); \
1081 out32((ChP)->IndexAddr,&(ChP)->R[0x04]); \
1091 #define sSetTxXONChar(ChP,CH) \ argument
1093 (ChP)->R[0x0b] = (CH); \
1094 out32((ChP)->IndexAddr,&(ChP)->R[0x08]); \
1107 #define sStartRxProcessor(ChP) out32((ChP)->IndexAddr,&(ChP)->R[0]) argument