297 	outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);  in mxser_enable_must_enchance_mode()
302 	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);  in mxser_enable_must_enchance_mode()
303 	outb(oldlcr, baseio + UART_LCR);  in mxser_enable_must_enchance_mode()
313 	outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);  in mxser_disable_must_enchance_mode()
318 	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);  in mxser_disable_must_enchance_mode()
319 	outb(oldlcr, baseio + UART_LCR);  in mxser_disable_must_enchance_mode()
329 	outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);  in mxser_set_must_xon1_value()
335 	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);  in mxser_set_must_xon1_value()
336 	outb(value, baseio + MOXA_MUST_XON1_REGISTER);  in mxser_set_must_xon1_value()
337 	outb(oldlcr, baseio + UART_LCR);  in mxser_set_must_xon1_value()
346 	outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);  in mxser_set_must_xoff1_value()
352 	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);  in mxser_set_must_xoff1_value()
353 	outb(value, baseio + MOXA_MUST_XOFF1_REGISTER);  in mxser_set_must_xoff1_value()
354 	outb(oldlcr, baseio + UART_LCR);  in mxser_set_must_xoff1_value()
363 	outb(MOXA_MUST_ENTER_ENCHANCE, info->ioaddr + UART_LCR);  in mxser_set_must_fifo_value()
369 	outb(efr, info->ioaddr + MOXA_MUST_EFR_REGISTER);  in mxser_set_must_fifo_value()
370 	outb((u8)info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTH_REGISTER);  in mxser_set_must_fifo_value()
371 	outb((u8)info->rx_trigger, info->ioaddr + MOXA_MUST_RBRTI_REGISTER);  in mxser_set_must_fifo_value()
372 	outb((u8)info->rx_low_water, info->ioaddr + MOXA_MUST_RBRTL_REGISTER);  in mxser_set_must_fifo_value()
373 	outb(oldlcr, info->ioaddr + UART_LCR);  in mxser_set_must_fifo_value()
382 	outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);  in mxser_set_must_enum_value()
388 	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);  in mxser_set_must_enum_value()
389 	outb(value, baseio + MOXA_MUST_ENUM_REGISTER);  in mxser_set_must_enum_value()
390 	outb(oldlcr, baseio + UART_LCR);  in mxser_set_must_enum_value()
400 	outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);  in mxser_get_must_hardware_id()
406 	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);  in mxser_get_must_hardware_id()
408 	outb(oldlcr, baseio + UART_LCR);  in mxser_get_must_hardware_id()
418 	outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);  in SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL()
423 	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);  in SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL()
424 	outb(oldlcr, baseio + UART_LCR);  in SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL()
433 	outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);  in mxser_enable_must_tx_software_flow_control()
439 	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);  in mxser_enable_must_tx_software_flow_control()
440 	outb(oldlcr, baseio + UART_LCR);  in mxser_enable_must_tx_software_flow_control()
449 	outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);  in mxser_disable_must_tx_software_flow_control()
454 	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);  in mxser_disable_must_tx_software_flow_control()
455 	outb(oldlcr, baseio + UART_LCR);  in mxser_disable_must_tx_software_flow_control()
464 	outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);  in mxser_enable_must_rx_software_flow_control()
470 	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);  in mxser_enable_must_rx_software_flow_control()
471 	outb(oldlcr, baseio + UART_LCR);  in mxser_enable_must_rx_software_flow_control()
480 	outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);  in mxser_disable_must_rx_software_flow_control()
485 	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);  in mxser_disable_must_rx_software_flow_control()
486 	outb(oldlcr, baseio + UART_LCR);  in mxser_disable_must_rx_software_flow_control()
495 	outb(0, io + UART_LCR);  in CheckIsMoxaMust()
498 	outb(0, io + UART_MCR);  in CheckIsMoxaMust()
501 		outb(oldmcr, io + UART_MCR);  in CheckIsMoxaMust()
563 		outb(inb(mp->ioaddr + UART_MCR) |  in mxser_dtr_rts()
566 		outb(inb(mp->ioaddr + UART_MCR)&~(UART_MCR_DTR | UART_MCR_RTS),  in mxser_dtr_rts()
601 		outb(info->MCR, info->ioaddr + UART_MCR);  in mxser_set_baud()
604 		outb(info->MCR, info->ioaddr + UART_MCR);  in mxser_set_baud()
610 	outb(cval | UART_LCR_DLAB, info->ioaddr + UART_LCR);	/* set DLAB */  in mxser_set_baud()
612 	outb(quot & 0xff, info->ioaddr + UART_DLL);	/* LS of divisor */  in mxser_set_baud()
613 	outb(quot >> 8, info->ioaddr + UART_DLM);	/* MS of divisor */  in mxser_set_baud()
614 	outb(cval, info->ioaddr + UART_LCR);	/* reset DLAB */  in mxser_set_baud()
725 						outb(info->IER & ~UART_IER_THRI,  in mxser_change_speed()
729 						outb(info->IER, info->ioaddr +  in mxser_change_speed()
740 						outb(info->IER, info->ioaddr +  in mxser_change_speed()
749 	outb(info->MCR, info->ioaddr + UART_MCR);  in mxser_change_speed()
756 	outb(info->IER, info->ioaddr + UART_IER);  in mxser_change_speed()
807 	outb(fcr, info->ioaddr + UART_FCR);	/* set fcr */  in mxser_change_speed()
808 	outb(cval, info->ioaddr + UART_LCR);  in mxser_change_speed()
840 					outb(port->IER & ~UART_IER_THRI,  in mxser_check_modem_status()
843 					outb(port->IER, port->ioaddr +  in mxser_check_modem_status()
854 					outb(port->IER, port->ioaddr +  in mxser_check_modem_status()
887 		outb((UART_FCR_CLEAR_RCVR |  in mxser_activate()
891 		outb((UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT),  in mxser_activate()
919 	outb(UART_LCR_WLEN8, info->ioaddr + UART_LCR);	/* reset DLAB */  in mxser_activate()
921 	outb(info->MCR, info->ioaddr + UART_MCR);  in mxser_activate()
930 	outb(info->IER, info->ioaddr + UART_IER);	/* enable interrupts */  in mxser_activate()
977 	outb(0x00, info->ioaddr + UART_IER);  in mxser_shutdown_port()
981 		outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT |  in mxser_shutdown_port()
985 		outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,  in mxser_shutdown_port()
1031 	outb((fcr | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT),  in mxser_flush_buffer()
1033 	outb(fcr, info->ioaddr + UART_FCR);  in mxser_flush_buffer()
1055 	outb(info->IER, info->ioaddr + UART_IER);  in mxser_close_port()
1132 			outb(info->IER & ~UART_IER_THRI, info->ioaddr +  in mxser_write()
1135 			outb(info->IER, info->ioaddr + UART_IER);  in mxser_write()
1163 			outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);  in mxser_put_char()
1165 			outb(info->IER, info->ioaddr + UART_IER);  in mxser_put_char()
1185 	outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);  in mxser_flush_chars()
1187 	outb(info->IER, info->ioaddr + UART_IER);  in mxser_flush_chars()
1376 	outb(info->MCR, info->ioaddr + UART_MCR);  in mxser_tiocmset()
1385 	outb(0, port);  in mxser_program_mode()
1386 	outb(0, port);  in mxser_program_mode()
1387 	outb(0, port);  in mxser_program_mode()
1390 	outb(0, port);  in mxser_program_mode()
1420 	outb(0xA5, port + 1);  in mxser_normal_mode()
1421 	outb(0x80, port + 3);  in mxser_normal_mode()
1422 	outb(12, port + 0);	/* 9600 bps */  in mxser_normal_mode()
1423 	outb(0, port + 1);  in mxser_normal_mode()
1424 	outb(0x03, port + 3);	/* 8 data bits */  in mxser_normal_mode()
1425 	outb(0x13, port + 4);	/* loop back mode */  in mxser_normal_mode()
1433 	outb(0x00, port + 4);  in mxser_normal_mode()
1460 			outb(CHIP_CS, port);  in mxser_read_register()
1462 				outb(CHIP_CS | CHIP_DO, port);  in mxser_read_register()
1463 				outb(CHIP_CS | CHIP_DO | CHIP_SK, port);	/* A? bit of read */  in mxser_read_register()
1465 				outb(CHIP_CS, port);  in mxser_read_register()
1466 				outb(CHIP_CS | CHIP_SK, port);	/* A? bit of read */  in mxser_read_register()
1472 			outb(CHIP_CS, port);  in mxser_read_register()
1473 			outb(CHIP_CS | CHIP_SK, port);  in mxser_read_register()
1478 		outb(0, port);  in mxser_read_register()
1701 			outb(val, info->opmode_ioaddr);  in mxser_ioctl()
1858 			outb(info->IER, info->ioaddr + UART_IER);  in mxser_stoprx()
1861 			outb(0, info->ioaddr + UART_IER);  in mxser_stoprx()
1863 			outb(info->IER, info->ioaddr + UART_IER);  in mxser_stoprx()
1869 		outb(info->MCR, info->ioaddr + UART_MCR);  in mxser_stoprx()
1894 				outb(info->IER, info->ioaddr + UART_IER);  in mxser_unthrottle()
1897 				outb(0, info->ioaddr + UART_IER);  in mxser_unthrottle()
1899 				outb(info->IER, info->ioaddr + UART_IER);  in mxser_unthrottle()
1906 		outb(info->MCR, info->ioaddr + UART_MCR);  in mxser_unthrottle()
1924 		outb(info->IER, info->ioaddr + UART_IER);  in mxser_stop()
1936 		outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);  in mxser_start()
1938 		outb(info->IER, info->ioaddr + UART_IER);  in mxser_start()
2052 		outb(inb(info->ioaddr + UART_LCR) | UART_LCR_SBC,  in mxser_rs_break()
2055 		outb(inb(info->ioaddr + UART_LCR) & ~UART_LCR_SBC,  in mxser_rs_break()
2106 			outb(0x23, port->ioaddr + UART_FCR);  in mxser_receive_chars()
2168 		outb(port->x_char, port->ioaddr + UART_TX);  in mxser_transmit_chars()
2185 		outb(port->IER, port->ioaddr + UART_IER);  in mxser_transmit_chars()
2192 		outb(port->port.xmit_buf[port->xmit_tail++],  in mxser_transmit_chars()
2209 		outb(port->IER, port->ioaddr + UART_IER);  in mxser_transmit_chars()
2263 					outb(0x27, port->ioaddr + UART_FCR);  in mxser_interrupt()
2418 		outb(inb(info->ioaddr + UART_IER) & 0xf0,  in mxser_initbrd()
2526 	outb(scratch2 | UART_LCR_DLAB, cap + UART_LCR);  in mxser_get_ISA_conf()
2527 	outb(0, cap + UART_EFR);	/* EFR is the same as FCR */  in mxser_get_ISA_conf()
2528 	outb(scratch2, cap + UART_LCR);  in mxser_get_ISA_conf()
2529 	outb(UART_FCR_ENABLE_FIFO, cap + UART_FCR);  in mxser_get_ISA_conf()
2638 		outb(0, ioaddress + 4);	/* default set to RS232 mode */  in mxser_probe()
2639 		outb(0, ioaddress + 0x0c);	/* default set to RS232 mode */  in mxser_probe()