Lines Matching refs:u32
70 u32 count:4; /* number of link controllers */
71 u32 unknown1:4;
72 u32 base_offset:8; /*
76 u32 length:12; /* link controller configuration area length */
77 u32 unknown2:4; /* TODO check that length is correct */
82 u32 unknown1:16;
83 u32 unknown2:14;
85 u32 unknown3:11;
87 u32 unknown4:2;
99 u32 unknown2:24;
104 u32 __unknown1:2;
105 u32 plug_events:5;
106 u32 __unknown2:25;
107 u32 __unknown3;
108 u32 __unknown4;
110 u32 __unknown5[7];
111 u32 drom_offset; /* 32 bit register, but eeprom addresses are 16 bit */
122 u32 first_cap_offset:8;
123 u32 upstream_port_number:6;
124 u32 max_port_number:6;
125 u32 depth:3;
126 u32 __unknown1:1;
127 u32 revision:8;
129 u32 route_lo;
131 u32 route_hi:31;
134 u32 plug_events_delay:8; /*
139 u32 __unknown4:16;
140 u32 thunderbolt_version:8;
162 u32 first_cap_offset:8;
163 u32 max_counters:11;
164 u32 __unknown1:5;
165 u32 revision:8;
168 u32 thunderbolt_version:8;
170 u32 __unknown2:20;
171 u32 port_number:6;
172 u32 __unknown3:6;
174 u32 nfc_credits;
176 u32 max_in_hop_id:11;
177 u32 max_out_hop_id:11;
178 u32 __unkown4:10;
180 u32 __unknown5;
182 u32 __unknown6;
189 u32 next_hop:11; /*
193 u32 out_port:6; /* next port of the path (on the same switch) */
194 u32 initial_credits:8;
195 u32 unknown1:6; /* set to zero */
199 u32 weight:4;
200 u32 unknown2:4; /* set to zero */
201 u32 priority:3;
203 u32 counter:11; /* index into TB_CFG_COUNTERS on this port */
209 u32 unknown3:4; /* set to zero */