Lines Matching refs:BIT
122 #define DRA752_BANDGAP_STATUS_1_ALERT_MASK BIT(31)
123 #define DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK BIT(5)
124 #define DRA752_BANDGAP_STATUS_1_COLD_CORE_MASK BIT(4)
125 #define DRA752_BANDGAP_STATUS_1_HOT_GPU_MASK BIT(3)
126 #define DRA752_BANDGAP_STATUS_1_COLD_GPU_MASK BIT(2)
127 #define DRA752_BANDGAP_STATUS_1_HOT_MPU_MASK BIT(1)
128 #define DRA752_BANDGAP_STATUS_1_COLD_MPU_MASK BIT(0)
131 #define DRA752_BANDGAP_CTRL_2_FREEZE_IVA_MASK BIT(22)
132 #define DRA752_BANDGAP_CTRL_2_FREEZE_DSPEVE_MASK BIT(21)
133 #define DRA752_BANDGAP_CTRL_2_CLEAR_IVA_MASK BIT(19)
134 #define DRA752_BANDGAP_CTRL_2_CLEAR_DSPEVE_MASK BIT(18)
135 #define DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_IVA_MASK BIT(16)
136 #define DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_DSPEVE_MASK BIT(15)
137 #define DRA752_BANDGAP_CTRL_2_MASK_HOT_IVA_MASK BIT(3)
138 #define DRA752_BANDGAP_CTRL_2_MASK_COLD_IVA_MASK BIT(2)
139 #define DRA752_BANDGAP_CTRL_2_MASK_HOT_DSPEVE_MASK BIT(1)
140 #define DRA752_BANDGAP_CTRL_2_MASK_COLD_DSPEVE_MASK BIT(0)
143 #define DRA752_BANDGAP_STATUS_2_HOT_IVA_MASK BIT(3)
144 #define DRA752_BANDGAP_STATUS_2_COLD_IVA_MASK BIT(2)
145 #define DRA752_BANDGAP_STATUS_2_HOT_DSPEVE_MASK BIT(1)
146 #define DRA752_BANDGAP_STATUS_2_COLD_DSPEVE_MASK BIT(0)
151 #define DRA752_BANDGAP_CTRL_1_FREEZE_CORE_MASK BIT(23)
152 #define DRA752_BANDGAP_CTRL_1_FREEZE_GPU_MASK BIT(22)
153 #define DRA752_BANDGAP_CTRL_1_FREEZE_MPU_MASK BIT(21)
154 #define DRA752_BANDGAP_CTRL_1_CLEAR_CORE_MASK BIT(20)
155 #define DRA752_BANDGAP_CTRL_1_CLEAR_GPU_MASK BIT(19)
156 #define DRA752_BANDGAP_CTRL_1_CLEAR_MPU_MASK BIT(18)
157 #define DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_CORE_MASK BIT(17)
158 #define DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_GPU_MASK BIT(16)
159 #define DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_MPU_MASK BIT(15)
160 #define DRA752_BANDGAP_CTRL_1_MASK_HOT_CORE_MASK BIT(5)
161 #define DRA752_BANDGAP_CTRL_1_MASK_COLD_CORE_MASK BIT(4)
162 #define DRA752_BANDGAP_CTRL_1_MASK_HOT_GPU_MASK BIT(3)
163 #define DRA752_BANDGAP_CTRL_1_MASK_COLD_GPU_MASK BIT(2)
164 #define DRA752_BANDGAP_CTRL_1_MASK_HOT_MPU_MASK BIT(1)
165 #define DRA752_BANDGAP_CTRL_1_MASK_COLD_MPU_MASK BIT(0)
168 #define DRA752_TEMP_SENSOR_TMPSOFF_MASK BIT(11)
169 #define DRA752_TEMP_SENSOR_EOCZ_MASK BIT(10)
177 #define DRA752_TSHUT_THRESHOLD_MUXCTRL_MASK BIT(31)