265 	u32 config_reg;  in zynqmp_qspi_init_hw()  local
287 	config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);  in zynqmp_qspi_init_hw()
288 	config_reg &= ~GQSPI_CFG_MODE_EN_MASK;  in zynqmp_qspi_init_hw()
290 	config_reg |= GQSPI_CFG_GEN_FIFO_START_MODE_MASK;  in zynqmp_qspi_init_hw()
292 	config_reg &= ~GQSPI_CFG_ENDIAN_MASK;  in zynqmp_qspi_init_hw()
294 	config_reg &= ~GQSPI_CFG_EN_POLL_TO_MASK;  in zynqmp_qspi_init_hw()
296 	config_reg |= GQSPI_CFG_WP_HOLD_MASK;  in zynqmp_qspi_init_hw()
298 	config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;  in zynqmp_qspi_init_hw()
300 	config_reg &= ~GQSPI_CFG_CLK_PHA_MASK;  in zynqmp_qspi_init_hw()
302 	config_reg &= ~GQSPI_CFG_CLK_POL_MASK;  in zynqmp_qspi_init_hw()
303 	zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);  in zynqmp_qspi_init_hw()
469 	u32 config_reg, req_hz, baud_rate_val = 0;  in zynqmp_qspi_setup_transfer()  local
485 	config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);  in zynqmp_qspi_setup_transfer()
488 	config_reg &= (~GQSPI_CFG_CLK_PHA_MASK) & (~GQSPI_CFG_CLK_POL_MASK);  in zynqmp_qspi_setup_transfer()
491 		config_reg |= GQSPI_CFG_CLK_PHA_MASK;  in zynqmp_qspi_setup_transfer()
493 		config_reg |= GQSPI_CFG_CLK_POL_MASK;  in zynqmp_qspi_setup_transfer()
495 	config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;  in zynqmp_qspi_setup_transfer()
496 	config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT);  in zynqmp_qspi_setup_transfer()
497 	zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);  in zynqmp_qspi_setup_transfer()
580 	u32 config_reg, genfifoentry;  in zynqmp_process_dma_irq()  local
594 		config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);  in zynqmp_process_dma_irq()
595 		config_reg &= ~GQSPI_CFG_MODE_EN_MASK;  in zynqmp_process_dma_irq()
596 		zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);  in zynqmp_process_dma_irq()
707 	u32 rx_bytes, rx_rem, config_reg;  in zynq_qspi_setuprxdma()  local
714 		config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);  in zynq_qspi_setuprxdma()
715 		config_reg &= ~GQSPI_CFG_MODE_EN_MASK;  in zynq_qspi_setuprxdma()
716 		zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);  in zynq_qspi_setuprxdma()
739 	config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);  in zynq_qspi_setuprxdma()
740 	config_reg &= ~GQSPI_CFG_MODE_EN_MASK;  in zynq_qspi_setuprxdma()
741 	config_reg |= GQSPI_CFG_MODE_EN_DMA_MASK;  in zynq_qspi_setuprxdma()
742 	zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);  in zynq_qspi_setuprxdma()
764 	u32 config_reg;  in zynqmp_qspi_txrxsetup()  local
776 			config_reg = zynqmp_gqspi_read(xqspi,  in zynqmp_qspi_txrxsetup()
778 			config_reg &= ~GQSPI_CFG_MODE_EN_MASK;  in zynqmp_qspi_txrxsetup()
780 								config_reg);  in zynqmp_qspi_txrxsetup()