150 static inline u32 tegra_sflash_readl(struct tegra_sflash_data *tsd,  in tegra_sflash_readl()  argument
153 	return readl(tsd->base + reg);  in tegra_sflash_readl()
156 static inline void tegra_sflash_writel(struct tegra_sflash_data *tsd,  in tegra_sflash_writel()  argument
159 	writel(val, tsd->base + reg);  in tegra_sflash_writel()
162 static void tegra_sflash_clear_status(struct tegra_sflash_data *tsd)  in tegra_sflash_clear_status()  argument
165 	tegra_sflash_writel(tsd, SPI_RDY | SPI_FIFO_ERROR, SPI_STATUS);  in tegra_sflash_clear_status()
169 	struct spi_device *spi, struct tegra_sflash_data *tsd,  in tegra_sflash_calculate_curr_xfer_param()  argument
172 	unsigned remain_len = t->len - tsd->cur_pos;  in tegra_sflash_calculate_curr_xfer_param()
175 	tsd->bytes_per_word = DIV_ROUND_UP(t->bits_per_word, 8);  in tegra_sflash_calculate_curr_xfer_param()
176 	max_word = remain_len / tsd->bytes_per_word;  in tegra_sflash_calculate_curr_xfer_param()
179 	tsd->curr_xfer_words = max_word;  in tegra_sflash_calculate_curr_xfer_param()
184 	struct tegra_sflash_data *tsd, struct spi_transfer *t)  in tegra_sflash_fill_tx_fifo_from_client_txbuf()  argument
188 	unsigned max_n_32bit = tsd->curr_xfer_words;  in tegra_sflash_fill_tx_fifo_from_client_txbuf()
189 	u8 *tx_buf = (u8 *)t->tx_buf + tsd->cur_tx_pos;  in tegra_sflash_fill_tx_fifo_from_client_txbuf()
193 	nbytes = max_n_32bit * tsd->bytes_per_word;  in tegra_sflash_fill_tx_fifo_from_client_txbuf()
195 	status = tegra_sflash_readl(tsd, SPI_STATUS);  in tegra_sflash_fill_tx_fifo_from_client_txbuf()
200 		for (i = 0; nbytes && (i < tsd->bytes_per_word);  in tegra_sflash_fill_tx_fifo_from_client_txbuf()
203 		tegra_sflash_writel(tsd, x, SPI_TX_FIFO);  in tegra_sflash_fill_tx_fifo_from_client_txbuf()
207 		status = tegra_sflash_readl(tsd, SPI_STATUS);  in tegra_sflash_fill_tx_fifo_from_client_txbuf()
209 	tsd->cur_tx_pos += max_n_32bit * tsd->bytes_per_word;  in tegra_sflash_fill_tx_fifo_from_client_txbuf()
214 		struct tegra_sflash_data *tsd, struct spi_transfer *t)  in tegra_sflash_read_rx_fifo_to_client_rxbuf()  argument
218 	u8 *rx_buf = (u8 *)t->rx_buf + tsd->cur_rx_pos;  in tegra_sflash_read_rx_fifo_to_client_rxbuf()
220 	status = tegra_sflash_readl(tsd, SPI_STATUS);  in tegra_sflash_read_rx_fifo_to_client_rxbuf()
223 		u32 x = tegra_sflash_readl(tsd, SPI_RX_FIFO);  in tegra_sflash_read_rx_fifo_to_client_rxbuf()
225 		for (i = 0; (i < tsd->bytes_per_word); i++)  in tegra_sflash_read_rx_fifo_to_client_rxbuf()
228 		status = tegra_sflash_readl(tsd, SPI_STATUS);  in tegra_sflash_read_rx_fifo_to_client_rxbuf()
230 	tsd->cur_rx_pos += read_words * tsd->bytes_per_word;  in tegra_sflash_read_rx_fifo_to_client_rxbuf()
235 		struct tegra_sflash_data *tsd, struct spi_transfer *t)  in tegra_sflash_start_cpu_based_transfer()  argument
240 	if (tsd->cur_direction & DATA_DIR_TX)  in tegra_sflash_start_cpu_based_transfer()
243 	if (tsd->cur_direction & DATA_DIR_RX)  in tegra_sflash_start_cpu_based_transfer()
246 	tegra_sflash_writel(tsd, val, SPI_DMA_CTL);  in tegra_sflash_start_cpu_based_transfer()
247 	tsd->dma_control_reg = val;  in tegra_sflash_start_cpu_based_transfer()
249 	if (tsd->cur_direction & DATA_DIR_TX)  in tegra_sflash_start_cpu_based_transfer()
250 		cur_words = tegra_sflash_fill_tx_fifo_from_client_txbuf(tsd, t);  in tegra_sflash_start_cpu_based_transfer()
252 		cur_words = tsd->curr_xfer_words;  in tegra_sflash_start_cpu_based_transfer()
254 	tegra_sflash_writel(tsd, val, SPI_DMA_CTL);  in tegra_sflash_start_cpu_based_transfer()
255 	tsd->dma_control_reg = val;  in tegra_sflash_start_cpu_based_transfer()
257 	tegra_sflash_writel(tsd, val, SPI_DMA_CTL);  in tegra_sflash_start_cpu_based_transfer()
265 	struct tegra_sflash_data *tsd = spi_master_get_devdata(spi->master);  in tegra_sflash_start_transfer_one()  local
270 	if (speed != tsd->cur_speed) {  in tegra_sflash_start_transfer_one()
271 		clk_set_rate(tsd->clk, speed);  in tegra_sflash_start_transfer_one()
272 		tsd->cur_speed = speed;  in tegra_sflash_start_transfer_one()
275 	tsd->cur_spi = spi;  in tegra_sflash_start_transfer_one()
276 	tsd->cur_pos = 0;  in tegra_sflash_start_transfer_one()
277 	tsd->cur_rx_pos = 0;  in tegra_sflash_start_transfer_one()
278 	tsd->cur_tx_pos = 0;  in tegra_sflash_start_transfer_one()
279 	tsd->curr_xfer = t;  in tegra_sflash_start_transfer_one()
280 	tegra_sflash_calculate_curr_xfer_param(spi, tsd, t);  in tegra_sflash_start_transfer_one()
282 		command = tsd->def_command_reg;  in tegra_sflash_start_transfer_one()
296 		command = tsd->command_reg;  in tegra_sflash_start_transfer_one()
302 	tsd->cur_direction = 0;  in tegra_sflash_start_transfer_one()
305 		tsd->cur_direction |= DATA_DIR_RX;  in tegra_sflash_start_transfer_one()
309 		tsd->cur_direction |= DATA_DIR_TX;  in tegra_sflash_start_transfer_one()
311 	tegra_sflash_writel(tsd, command, SPI_COMMAND);  in tegra_sflash_start_transfer_one()
312 	tsd->command_reg = command;  in tegra_sflash_start_transfer_one()
314 	return tegra_sflash_start_cpu_based_transfer(tsd, t);  in tegra_sflash_start_transfer_one()
322 	struct tegra_sflash_data *tsd = spi_master_get_devdata(master);  in tegra_sflash_transfer_one_message()  local
331 		reinit_completion(&tsd->xfer_completion);  in tegra_sflash_transfer_one_message()
335 			dev_err(tsd->dev,  in tegra_sflash_transfer_one_message()
340 		ret = wait_for_completion_timeout(&tsd->xfer_completion,  in tegra_sflash_transfer_one_message()
343 			dev_err(tsd->dev,  in tegra_sflash_transfer_one_message()
349 		if (tsd->tx_status ||  tsd->rx_status) {  in tegra_sflash_transfer_one_message()
350 			dev_err(tsd->dev, "Error in Transfer\n");  in tegra_sflash_transfer_one_message()
356 			tegra_sflash_writel(tsd, tsd->def_command_reg,  in tegra_sflash_transfer_one_message()
363 	tegra_sflash_writel(tsd, tsd->def_command_reg, SPI_COMMAND);  in tegra_sflash_transfer_one_message()
369 static irqreturn_t handle_cpu_based_xfer(struct tegra_sflash_data *tsd)  in handle_cpu_based_xfer()  argument
371 	struct spi_transfer *t = tsd->curr_xfer;  in handle_cpu_based_xfer()
374 	spin_lock_irqsave(&tsd->lock, flags);  in handle_cpu_based_xfer()
375 	if (tsd->tx_status || tsd->rx_status || (tsd->status_reg & SPI_BSY)) {  in handle_cpu_based_xfer()
376 		dev_err(tsd->dev,  in handle_cpu_based_xfer()
377 			"CpuXfer ERROR bit set 0x%x\n", tsd->status_reg);  in handle_cpu_based_xfer()
378 		dev_err(tsd->dev,  in handle_cpu_based_xfer()
379 			"CpuXfer 0x%08x:0x%08x\n", tsd->command_reg,  in handle_cpu_based_xfer()
380 				tsd->dma_control_reg);  in handle_cpu_based_xfer()
381 		reset_control_assert(tsd->rst);  in handle_cpu_based_xfer()
383 		reset_control_deassert(tsd->rst);  in handle_cpu_based_xfer()
384 		complete(&tsd->xfer_completion);  in handle_cpu_based_xfer()
388 	if (tsd->cur_direction & DATA_DIR_RX)  in handle_cpu_based_xfer()
389 		tegra_sflash_read_rx_fifo_to_client_rxbuf(tsd, t);  in handle_cpu_based_xfer()
391 	if (tsd->cur_direction & DATA_DIR_TX)  in handle_cpu_based_xfer()
392 		tsd->cur_pos = tsd->cur_tx_pos;  in handle_cpu_based_xfer()
394 		tsd->cur_pos = tsd->cur_rx_pos;  in handle_cpu_based_xfer()
396 	if (tsd->cur_pos == t->len) {  in handle_cpu_based_xfer()
397 		complete(&tsd->xfer_completion);  in handle_cpu_based_xfer()
401 	tegra_sflash_calculate_curr_xfer_param(tsd->cur_spi, tsd, t);  in handle_cpu_based_xfer()
402 	tegra_sflash_start_cpu_based_transfer(tsd, t);  in handle_cpu_based_xfer()
404 	spin_unlock_irqrestore(&tsd->lock, flags);  in handle_cpu_based_xfer()
410 	struct tegra_sflash_data *tsd = context_data;  in tegra_sflash_isr()  local
412 	tsd->status_reg = tegra_sflash_readl(tsd, SPI_STATUS);  in tegra_sflash_isr()
413 	if (tsd->cur_direction & DATA_DIR_TX)  in tegra_sflash_isr()
414 		tsd->tx_status = tsd->status_reg & SPI_TX_OVF;  in tegra_sflash_isr()
416 	if (tsd->cur_direction & DATA_DIR_RX)  in tegra_sflash_isr()
417 		tsd->rx_status = tsd->status_reg & SPI_RX_UNF;  in tegra_sflash_isr()
418 	tegra_sflash_clear_status(tsd);  in tegra_sflash_isr()
420 	return handle_cpu_based_xfer(tsd);  in tegra_sflash_isr()
432 	struct tegra_sflash_data	*tsd;  in tegra_sflash_probe()  local
443 	master = spi_alloc_master(&pdev->dev, sizeof(*tsd));  in tegra_sflash_probe()
456 	tsd = spi_master_get_devdata(master);  in tegra_sflash_probe()
457 	tsd->master = master;  in tegra_sflash_probe()
458 	tsd->dev = &pdev->dev;  in tegra_sflash_probe()
459 	spin_lock_init(&tsd->lock);  in tegra_sflash_probe()
461 	if (of_property_read_u32(tsd->dev->of_node, "spi-max-frequency",  in tegra_sflash_probe()
466 	tsd->base = devm_ioremap_resource(&pdev->dev, r);  in tegra_sflash_probe()
467 	if (IS_ERR(tsd->base)) {  in tegra_sflash_probe()
468 		ret = PTR_ERR(tsd->base);  in tegra_sflash_probe()
472 	tsd->irq = platform_get_irq(pdev, 0);  in tegra_sflash_probe()
473 	ret = request_irq(tsd->irq, tegra_sflash_isr, 0,  in tegra_sflash_probe()
474 			dev_name(&pdev->dev), tsd);  in tegra_sflash_probe()
477 					tsd->irq);  in tegra_sflash_probe()
481 	tsd->clk = devm_clk_get(&pdev->dev, NULL);  in tegra_sflash_probe()
482 	if (IS_ERR(tsd->clk)) {  in tegra_sflash_probe()
484 		ret = PTR_ERR(tsd->clk);  in tegra_sflash_probe()
488 	tsd->rst = devm_reset_control_get(&pdev->dev, "spi");  in tegra_sflash_probe()
489 	if (IS_ERR(tsd->rst)) {  in tegra_sflash_probe()
491 		ret = PTR_ERR(tsd->rst);  in tegra_sflash_probe()
495 	init_completion(&tsd->xfer_completion);  in tegra_sflash_probe()
510 	reset_control_assert(tsd->rst);  in tegra_sflash_probe()
512 	reset_control_deassert(tsd->rst);  in tegra_sflash_probe()
514 	tsd->def_command_reg  = SPI_M_S | SPI_CS_SW;  in tegra_sflash_probe()
515 	tegra_sflash_writel(tsd, tsd->def_command_reg, SPI_COMMAND);  in tegra_sflash_probe()
531 	free_irq(tsd->irq, tsd);  in tegra_sflash_probe()
540 	struct tegra_sflash_data	*tsd = spi_master_get_devdata(master);  in tegra_sflash_remove()  local
542 	free_irq(tsd->irq, tsd);  in tegra_sflash_remove()
562 	struct tegra_sflash_data *tsd = spi_master_get_devdata(master);  in tegra_sflash_resume()  local
570 	tegra_sflash_writel(tsd, tsd->command_reg, SPI_COMMAND);  in tegra_sflash_resume()
580 	struct tegra_sflash_data *tsd = spi_master_get_devdata(master);  in tegra_sflash_runtime_suspend()  local
583 	tegra_sflash_readl(tsd, SPI_COMMAND);  in tegra_sflash_runtime_suspend()
585 	clk_disable_unprepare(tsd->clk);  in tegra_sflash_runtime_suspend()
592 	struct tegra_sflash_data *tsd = spi_master_get_devdata(master);  in tegra_sflash_runtime_resume()  local
595 	ret = clk_prepare_enable(tsd->clk);  in tegra_sflash_runtime_resume()
597 		dev_err(tsd->dev, "clk_prepare failed: %d\n", ret);  in tegra_sflash_runtime_resume()