Lines Matching refs:pxa2xx_spi_read
189 return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask; in pxa2xx_spi_txfifo_full()
374 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) in pxa2xx_spi_flush()
375 pxa2xx_spi_read(drv_data, SSDR); in pxa2xx_spi_flush()
376 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit); in pxa2xx_spi_flush()
400 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) in null_reader()
402 pxa2xx_spi_read(drv_data, SSDR); in null_reader()
423 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) in u8_reader()
425 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); in u8_reader()
446 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) in u16_reader()
448 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); in u16_reader()
469 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) in u32_reader()
471 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); in u32_reader()
550 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1; in reset_sccr1()
565 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); in int_error_stop()
598 u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ? in interrupt_transfer()
601 u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask; in interrupt_transfer()
633 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); in interrupt_transfer()
688 status = pxa2xx_spi_read(drv_data, SSSR); in ssp_int()
692 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); in ssp_int()
708 pxa2xx_spi_read(drv_data, SSCR0) in ssp_int()
711 pxa2xx_spi_read(drv_data, SSCR1) in ssp_int()
1044 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff) in pump_transfers()
1048 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff) in pump_transfers()
1055 (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate)) in pump_transfers()
1059 if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0) in pump_transfers()
1060 || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask) in pump_transfers()
1110 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); in pxa2xx_spi_unprepare_transfer()