1611 				struct pl022_config_chip const *chip_info)  in verify_controller_parameters()  argument
1613 	if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI)  in verify_controller_parameters()
1614 	    || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) {  in verify_controller_parameters()
1619 	if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) &&  in verify_controller_parameters()
1626 	if ((chip_info->hierarchy != SSP_MASTER)  in verify_controller_parameters()
1627 	    && (chip_info->hierarchy != SSP_SLAVE)) {  in verify_controller_parameters()
1632 	if ((chip_info->com_mode != INTERRUPT_TRANSFER)  in verify_controller_parameters()
1633 	    && (chip_info->com_mode != DMA_TRANSFER)  in verify_controller_parameters()
1634 	    && (chip_info->com_mode != POLLING_TRANSFER)) {  in verify_controller_parameters()
1639 	switch (chip_info->rx_lev_trig) {  in verify_controller_parameters()
1664 	switch (chip_info->tx_lev_trig) {  in verify_controller_parameters()
1689 	if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) {  in verify_controller_parameters()
1690 		if ((chip_info->ctrl_len < SSP_BITS_4)  in verify_controller_parameters()
1691 		    || (chip_info->ctrl_len > SSP_BITS_32)) {  in verify_controller_parameters()
1696 		if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO)  in verify_controller_parameters()
1697 		    && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) {  in verify_controller_parameters()
1704 			if ((chip_info->duplex !=  in verify_controller_parameters()
1706 			    && (chip_info->duplex !=  in verify_controller_parameters()
1713 			if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)  in verify_controller_parameters()
1836 	struct pl022_config_chip const *chip_info;  in pl022_setup()  local
1861 	chip_info = spi->controller_data;  in pl022_setup()
1863 	if (chip_info == NULL) {  in pl022_setup()
1883 			chip_info = &chip_info_dt;  in pl022_setup()
1885 			chip_info = &pl022_default_chip_info;  in pl022_setup()
1898 	if ((0 == chip_info->clk_freq.cpsdvsr)  in pl022_setup()
1899 	    && (0 == chip_info->clk_freq.scr)) {  in pl022_setup()
1906 		memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq));  in pl022_setup()
1919 	status = verify_controller_parameters(pl022, chip_info);  in pl022_setup()
1925 	pl022->rx_lev_trig = chip_info->rx_lev_trig;  in pl022_setup()
1926 	pl022->tx_lev_trig = chip_info->tx_lev_trig;  in pl022_setup()
1929 	chip->xfer_type = chip_info->com_mode;  in pl022_setup()
1930 	if (!chip_info->cs_control) {  in pl022_setup()
1936 		chip->cs_control = chip_info->cs_control;  in pl022_setup()
1967 	if ((chip_info->com_mode == DMA_TRANSFER)  in pl022_setup()
1992 			SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay,  in pl022_setup()
1996 			SSP_WRITE_BITS(chip->cr0, chip_info->duplex,  in pl022_setup()
1998 			SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len,  in pl022_setup()
2000 			SSP_WRITE_BITS(chip->cr0, chip_info->iface,  in pl022_setup()
2002 			SSP_WRITE_BITS(chip->cr1, chip_info->wait_state,  in pl022_setup()
2017 		SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig,  in pl022_setup()
2019 		SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig,  in pl022_setup()
2024 		SSP_WRITE_BITS(chip->cr0, chip_info->iface,  in pl022_setup()
2051 	SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2);  in pl022_setup()
2052 	SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD,  in pl022_setup()