52 #define SSP_WRITE_BITS(reg, val, mask, sb) \  macro
1971 		SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,  in pl022_setup()
1973 		SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,  in pl022_setup()
1978 		SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,  in pl022_setup()
1980 		SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,  in pl022_setup()
1992 			SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay,  in pl022_setup()
1996 			SSP_WRITE_BITS(chip->cr0, chip_info->duplex,  in pl022_setup()
1998 			SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len,  in pl022_setup()
2000 			SSP_WRITE_BITS(chip->cr0, chip_info->iface,  in pl022_setup()
2002 			SSP_WRITE_BITS(chip->cr1, chip_info->wait_state,  in pl022_setup()
2005 		SSP_WRITE_BITS(chip->cr0, bits - 1,  in pl022_setup()
2015 		SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4);  in pl022_setup()
2016 		SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5);  in pl022_setup()
2017 		SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig,  in pl022_setup()
2019 		SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig,  in pl022_setup()
2022 		SSP_WRITE_BITS(chip->cr0, bits - 1,  in pl022_setup()
2024 		SSP_WRITE_BITS(chip->cr0, chip_info->iface,  in pl022_setup()
2033 	SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6);  in pl022_setup()
2039 	SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7);  in pl022_setup()
2041 	SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8);  in pl022_setup()
2048 		SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0);  in pl022_setup()
2050 	SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1);  in pl022_setup()
2051 	SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2);  in pl022_setup()
2052 	SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD,  in pl022_setup()