169 static inline void mcspi_write_cs_reg(const struct spi_device *spi,  in mcspi_write_cs_reg()  argument
172 	struct omap2_mcspi_cs	*cs = spi->controller_state;  in mcspi_write_cs_reg()
177 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)  in mcspi_read_cs_reg()  argument
179 	struct omap2_mcspi_cs	*cs = spi->controller_state;  in mcspi_read_cs_reg()
184 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)  in mcspi_cached_chconf0()  argument
186 	struct omap2_mcspi_cs *cs = spi->controller_state;  in mcspi_cached_chconf0()
191 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)  in mcspi_write_chconf0()  argument
193 	struct omap2_mcspi_cs *cs = spi->controller_state;  in mcspi_write_chconf0()
196 	mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);  in mcspi_write_chconf0()
197 	mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);  in mcspi_write_chconf0()
210 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,  in omap2_mcspi_set_dma_req()  argument
215 	l = mcspi_cached_chconf0(spi);  in omap2_mcspi_set_dma_req()
227 	mcspi_write_chconf0(spi, l);  in omap2_mcspi_set_dma_req()
230 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)  in omap2_mcspi_set_enable()  argument
232 	struct omap2_mcspi_cs *cs = spi->controller_state;  in omap2_mcspi_set_enable()
241 	mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);  in omap2_mcspi_set_enable()
243 	mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);  in omap2_mcspi_set_enable()
246 static void omap2_mcspi_set_cs(struct spi_device *spi, bool enable)  in omap2_mcspi_set_cs()  argument
248 	struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);  in omap2_mcspi_set_cs()
255 	if (spi->mode & SPI_CS_HIGH)  in omap2_mcspi_set_cs()
258 	if (spi->controller_state) {  in omap2_mcspi_set_cs()
265 		l = mcspi_cached_chconf0(spi);  in omap2_mcspi_set_cs()
272 		mcspi_write_chconf0(spi, l);  in omap2_mcspi_set_cs()
297 static void omap2_mcspi_set_fifo(const struct spi_device *spi,  in omap2_mcspi_set_fifo()  argument
300 	struct spi_master *master = spi->master;  in omap2_mcspi_set_fifo()
301 	struct omap2_mcspi_cs *cs = spi->controller_state;  in omap2_mcspi_set_fifo()
309 	chconf = mcspi_cached_chconf0(spi);  in omap2_mcspi_set_fifo()
339 		mcspi_write_chconf0(spi, chconf);  in omap2_mcspi_set_fifo()
352 	mcspi_write_chconf0(spi, chconf);  in omap2_mcspi_set_fifo()
389 	struct spi_device *spi = data;  in omap2_mcspi_rx_callback()  local
390 	struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);  in omap2_mcspi_rx_callback()
391 	struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];  in omap2_mcspi_rx_callback()
394 	omap2_mcspi_set_dma_req(spi, 1, 0);  in omap2_mcspi_rx_callback()
401 	struct spi_device *spi = data;  in omap2_mcspi_tx_callback()  local
402 	struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);  in omap2_mcspi_tx_callback()
403 	struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];  in omap2_mcspi_tx_callback()
406 	omap2_mcspi_set_dma_req(spi, 0, 0);  in omap2_mcspi_tx_callback()
411 static void omap2_mcspi_tx_dma(struct spi_device *spi,  in omap2_mcspi_tx_dma()  argument
419 	mcspi = spi_master_get_devdata(spi->master);  in omap2_mcspi_tx_dma()
420 	mcspi_dma = &mcspi->dma_channels[spi->chip_select];  in omap2_mcspi_tx_dma()
437 			tx->callback_param = spi;  in omap2_mcspi_tx_dma()
444 	omap2_mcspi_set_dma_req(spi, 0, 1);  in omap2_mcspi_tx_dma()
449 omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,  in omap2_mcspi_rx_dma()  argument
459 	struct omap2_mcspi_cs	*cs = spi->controller_state;  in omap2_mcspi_rx_dma()
460 	mcspi = spi_master_get_devdata(spi->master);  in omap2_mcspi_rx_dma()
461 	mcspi_dma = &mcspi->dma_channels[spi->chip_select];  in omap2_mcspi_rx_dma()
469 	l = mcspi_cached_chconf0(spi);  in omap2_mcspi_rx_dma()
496 			tx->callback_param = spi;  in omap2_mcspi_rx_dma()
504 	omap2_mcspi_set_dma_req(spi, 1, 1);  in omap2_mcspi_rx_dma()
513 	omap2_mcspi_set_enable(spi, 0);  in omap2_mcspi_rx_dma()
520 		if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)  in omap2_mcspi_rx_dma()
524 			w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);  in omap2_mcspi_rx_dma()
533 			dev_err(&spi->dev, "DMA RX penultimate word empty\n");  in omap2_mcspi_rx_dma()
535 			omap2_mcspi_set_enable(spi, 1);  in omap2_mcspi_rx_dma()
539 	if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)  in omap2_mcspi_rx_dma()
543 		w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);  in omap2_mcspi_rx_dma()
551 		dev_err(&spi->dev, "DMA RX last word empty\n");  in omap2_mcspi_rx_dma()
554 	omap2_mcspi_set_enable(spi, 1);  in omap2_mcspi_rx_dma()
559 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)  in omap2_mcspi_txrx_dma()  argument
562 	struct omap2_mcspi_cs	*cs = spi->controller_state;  in omap2_mcspi_txrx_dma()
576 	mcspi = spi_master_get_devdata(spi->master);  in omap2_mcspi_txrx_dma()
577 	mcspi_dma = &mcspi->dma_channels[spi->chip_select];  in omap2_mcspi_txrx_dma()
578 	l = mcspi_cached_chconf0(spi);  in omap2_mcspi_txrx_dma()
614 		omap2_mcspi_tx_dma(spi, xfer, cfg);  in omap2_mcspi_txrx_dma()
617 		count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);  in omap2_mcspi_txrx_dma()
629 				dev_err(&spi->dev, "EOW timed out\n");  in omap2_mcspi_txrx_dma()
642 					dev_err(&spi->dev, "TXFFE timed out\n");  in omap2_mcspi_txrx_dma()
647 					dev_err(&spi->dev, "TXS timed out\n");  in omap2_mcspi_txrx_dma()
652 				dev_err(&spi->dev, "EOT timed out\n");  in omap2_mcspi_txrx_dma()
659 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)  in omap2_mcspi_txrx_pio()  argument
662 	struct omap2_mcspi_cs	*cs = spi->controller_state;  in omap2_mcspi_txrx_pio()
671 	mcspi = spi_master_get_devdata(spi->master);  in omap2_mcspi_txrx_pio()
676 	l = mcspi_cached_chconf0(spi);  in omap2_mcspi_txrx_pio()
699 					dev_err(&spi->dev, "TXS timed out\n");  in omap2_mcspi_txrx_pio()
702 				dev_vdbg(&spi->dev, "write-%d %02x\n",  in omap2_mcspi_txrx_pio()
709 					dev_err(&spi->dev, "RXS timed out\n");  in omap2_mcspi_txrx_pio()
715 					omap2_mcspi_set_enable(spi, 0);  in omap2_mcspi_txrx_pio()
717 					dev_vdbg(&spi->dev, "read-%d %02x\n",  in omap2_mcspi_txrx_pio()
721 						dev_err(&spi->dev,  in omap2_mcspi_txrx_pio()
727 					omap2_mcspi_set_enable(spi, 0);  in omap2_mcspi_txrx_pio()
731 				dev_vdbg(&spi->dev, "read-%d %02x\n",  in omap2_mcspi_txrx_pio()
746 					dev_err(&spi->dev, "TXS timed out\n");  in omap2_mcspi_txrx_pio()
749 				dev_vdbg(&spi->dev, "write-%d %04x\n",  in omap2_mcspi_txrx_pio()
756 					dev_err(&spi->dev, "RXS timed out\n");  in omap2_mcspi_txrx_pio()
762 					omap2_mcspi_set_enable(spi, 0);  in omap2_mcspi_txrx_pio()
764 					dev_vdbg(&spi->dev, "read-%d %04x\n",  in omap2_mcspi_txrx_pio()
768 						dev_err(&spi->dev,  in omap2_mcspi_txrx_pio()
774 					omap2_mcspi_set_enable(spi, 0);  in omap2_mcspi_txrx_pio()
778 				dev_vdbg(&spi->dev, "read-%d %04x\n",  in omap2_mcspi_txrx_pio()
793 					dev_err(&spi->dev, "TXS timed out\n");  in omap2_mcspi_txrx_pio()
796 				dev_vdbg(&spi->dev, "write-%d %08x\n",  in omap2_mcspi_txrx_pio()
803 					dev_err(&spi->dev, "RXS timed out\n");  in omap2_mcspi_txrx_pio()
809 					omap2_mcspi_set_enable(spi, 0);  in omap2_mcspi_txrx_pio()
811 					dev_vdbg(&spi->dev, "read-%d %08x\n",  in omap2_mcspi_txrx_pio()
815 						dev_err(&spi->dev,  in omap2_mcspi_txrx_pio()
821 					omap2_mcspi_set_enable(spi, 0);  in omap2_mcspi_txrx_pio()
825 				dev_vdbg(&spi->dev, "read-%d %08x\n",  in omap2_mcspi_txrx_pio()
835 			dev_err(&spi->dev, "TXS timed out\n");  in omap2_mcspi_txrx_pio()
838 			dev_err(&spi->dev, "EOT timed out\n");  in omap2_mcspi_txrx_pio()
844 		omap2_mcspi_set_enable(spi, 0);  in omap2_mcspi_txrx_pio()
847 	omap2_mcspi_set_enable(spi, 1);  in omap2_mcspi_txrx_pio()
863 static int omap2_mcspi_setup_transfer(struct spi_device *spi,  in omap2_mcspi_setup_transfer()  argument
866 	struct omap2_mcspi_cs *cs = spi->controller_state;  in omap2_mcspi_setup_transfer()
870 	u8 word_len = spi->bits_per_word;  in omap2_mcspi_setup_transfer()
871 	u32 speed_hz = spi->max_speed_hz;  in omap2_mcspi_setup_transfer()
873 	mcspi = spi_master_get_devdata(spi->master);  in omap2_mcspi_setup_transfer()
897 	l = mcspi_cached_chconf0(spi);  in omap2_mcspi_setup_transfer()
917 	if (!(spi->mode & SPI_CS_HIGH))  in omap2_mcspi_setup_transfer()
932 		mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);  in omap2_mcspi_setup_transfer()
936 	if (spi->mode & SPI_CPOL)  in omap2_mcspi_setup_transfer()
940 	if (spi->mode & SPI_CPHA)  in omap2_mcspi_setup_transfer()
945 	mcspi_write_chconf0(spi, l);  in omap2_mcspi_setup_transfer()
947 	cs->mode = spi->mode;  in omap2_mcspi_setup_transfer()
949 	dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",  in omap2_mcspi_setup_transfer()
951 			(spi->mode & SPI_CPHA) ? "trailing" : "leading",  in omap2_mcspi_setup_transfer()
952 			(spi->mode & SPI_CPOL) ? "inverted" : "normal");  in omap2_mcspi_setup_transfer()
961 static int omap2_mcspi_request_dma(struct spi_device *spi)  in omap2_mcspi_request_dma()  argument
963 	struct spi_master	*master = spi->master;  in omap2_mcspi_request_dma()
970 	mcspi_dma = mcspi->dma_channels + spi->chip_select;  in omap2_mcspi_request_dma()
1001 	dev_warn(&spi->dev, "not using DMA for McSPI\n");  in omap2_mcspi_request_dma()
1005 static int omap2_mcspi_setup(struct spi_device *spi)  in omap2_mcspi_setup()  argument
1008 	struct omap2_mcspi	*mcspi = spi_master_get_devdata(spi->master);  in omap2_mcspi_setup()
1011 	struct omap2_mcspi_cs	*cs = spi->controller_state;  in omap2_mcspi_setup()
1013 	mcspi_dma = &mcspi->dma_channels[spi->chip_select];  in omap2_mcspi_setup()
1019 		cs->base = mcspi->base + spi->chip_select * 0x14;  in omap2_mcspi_setup()
1020 		cs->phys = mcspi->phys + spi->chip_select * 0x14;  in omap2_mcspi_setup()
1024 		spi->controller_state = cs;  in omap2_mcspi_setup()
1028 		if (gpio_is_valid(spi->cs_gpio)) {  in omap2_mcspi_setup()
1029 			ret = gpio_request(spi->cs_gpio, dev_name(&spi->dev));  in omap2_mcspi_setup()
1031 				dev_err(&spi->dev, "failed to request gpio\n");  in omap2_mcspi_setup()
1034 			gpio_direction_output(spi->cs_gpio,  in omap2_mcspi_setup()
1035 					 !(spi->mode & SPI_CS_HIGH));  in omap2_mcspi_setup()
1040 		ret = omap2_mcspi_request_dma(spi);  in omap2_mcspi_setup()
1049 	ret = omap2_mcspi_setup_transfer(spi, NULL);  in omap2_mcspi_setup()
1056 static void omap2_mcspi_cleanup(struct spi_device *spi)  in omap2_mcspi_cleanup()  argument
1062 	mcspi = spi_master_get_devdata(spi->master);  in omap2_mcspi_cleanup()
1064 	if (spi->controller_state) {  in omap2_mcspi_cleanup()
1066 		cs = spi->controller_state;  in omap2_mcspi_cleanup()
1072 	if (spi->chip_select < spi->master->num_chipselect) {  in omap2_mcspi_cleanup()
1073 		mcspi_dma = &mcspi->dma_channels[spi->chip_select];  in omap2_mcspi_cleanup()
1085 	if (gpio_is_valid(spi->cs_gpio))  in omap2_mcspi_cleanup()
1086 		gpio_free(spi->cs_gpio);  in omap2_mcspi_cleanup()
1090 		struct spi_device *spi, struct spi_transfer *t)  in omap2_mcspi_work_one()  argument
1108 	master = spi->master;  in omap2_mcspi_work_one()
1109 	mcspi_dma = mcspi->dma_channels + spi->chip_select;  in omap2_mcspi_work_one()
1110 	cs = spi->controller_state;  in omap2_mcspi_work_one()
1111 	cd = spi->controller_data;  in omap2_mcspi_work_one()
1120 	if (spi->mode != cs->mode)  in omap2_mcspi_work_one()
1123 	omap2_mcspi_set_enable(spi, 0);  in omap2_mcspi_work_one()
1125 	if (gpio_is_valid(spi->cs_gpio))  in omap2_mcspi_work_one()
1126 		omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH);  in omap2_mcspi_work_one()
1129 	    (t->speed_hz != spi->max_speed_hz) ||  in omap2_mcspi_work_one()
1130 	    (t->bits_per_word != spi->bits_per_word)) {  in omap2_mcspi_work_one()
1132 		status = omap2_mcspi_setup_transfer(spi, t);  in omap2_mcspi_work_one()
1135 		if (t->speed_hz == spi->max_speed_hz &&  in omap2_mcspi_work_one()
1136 		    t->bits_per_word == spi->bits_per_word)  in omap2_mcspi_work_one()
1144 			mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);  in omap2_mcspi_work_one()
1147 	chconf = mcspi_cached_chconf0(spi);  in omap2_mcspi_work_one()
1162 	mcspi_write_chconf0(spi, chconf);  in omap2_mcspi_work_one()
1169 			omap2_mcspi_set_fifo(spi, t, 1);  in omap2_mcspi_work_one()
1171 		omap2_mcspi_set_enable(spi, 1);  in omap2_mcspi_work_one()
1180 			count = omap2_mcspi_txrx_dma(spi, t);  in omap2_mcspi_work_one()
1182 			count = omap2_mcspi_txrx_pio(spi, t);  in omap2_mcspi_work_one()
1190 	omap2_mcspi_set_enable(spi, 0);  in omap2_mcspi_work_one()
1193 		omap2_mcspi_set_fifo(spi, t, 0);  in omap2_mcspi_work_one()
1199 		status = omap2_mcspi_setup_transfer(spi, NULL);  in omap2_mcspi_work_one()
1207 			mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);  in omap2_mcspi_work_one()
1210 	omap2_mcspi_set_enable(spi, 0);  in omap2_mcspi_work_one()
1212 	if (gpio_is_valid(spi->cs_gpio))  in omap2_mcspi_work_one()
1213 		omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH));  in omap2_mcspi_work_one()
1216 		omap2_mcspi_set_fifo(spi, t, 0);  in omap2_mcspi_work_one()
1234 		if (msg->spi->controller_state == cs)  in omap2_mcspi_prepare_message()
1249 		struct spi_device *spi, struct spi_transfer *t)  in omap2_mcspi_transfer_one()  argument
1258 	mcspi_dma = mcspi->dma_channels + spi->chip_select;  in omap2_mcspi_transfer_one()
1296 	return omap2_mcspi_work_one(mcspi, spi, t);  in omap2_mcspi_transfer_one()