92 	int (*dma_init)(struct dw_spi *dws);
93 	void (*dma_exit)(struct dw_spi *dws);
94 	int (*dma_setup)(struct dw_spi *dws, struct spi_transfer *xfer);
97 	int (*dma_transfer)(struct dw_spi *dws, struct spi_transfer *xfer);
98 	void (*dma_stop)(struct dw_spi *dws);
125 	irqreturn_t		(*transfer_handler)(struct dw_spi *dws);
144 static inline u32 dw_readl(struct dw_spi *dws, u32 offset)  in dw_readl()  argument
146 	return __raw_readl(dws->regs + offset);  in dw_readl()
149 static inline u16 dw_readw(struct dw_spi *dws, u32 offset)  in dw_readw()  argument
151 	return __raw_readw(dws->regs + offset);  in dw_readw()
154 static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)  in dw_writel()  argument
156 	__raw_writel(val, dws->regs + offset);  in dw_writel()
159 static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val)  in dw_writew()  argument
161 	__raw_writew(val, dws->regs + offset);  in dw_writew()
164 static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset)  in dw_read_io_reg()  argument
166 	switch (dws->reg_io_width) {  in dw_read_io_reg()
168 		return dw_readw(dws, offset);  in dw_read_io_reg()
171 		return dw_readl(dws, offset);  in dw_read_io_reg()
175 static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val)  in dw_write_io_reg()  argument
177 	switch (dws->reg_io_width) {  in dw_write_io_reg()
179 		dw_writew(dws, offset, val);  in dw_write_io_reg()
183 		dw_writel(dws, offset, val);  in dw_write_io_reg()
188 static inline void spi_enable_chip(struct dw_spi *dws, int enable)  in spi_enable_chip()  argument
190 	dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));  in spi_enable_chip()
193 static inline void spi_set_clk(struct dw_spi *dws, u16 div)  in spi_set_clk()  argument
195 	dw_writel(dws, DW_SPI_BAUDR, div);  in spi_set_clk()
199 static inline void spi_mask_intr(struct dw_spi *dws, u32 mask)  in spi_mask_intr()  argument
203 	new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask;  in spi_mask_intr()
204 	dw_writel(dws, DW_SPI_IMR, new_mask);  in spi_mask_intr()
208 static inline void spi_umask_intr(struct dw_spi *dws, u32 mask)  in spi_umask_intr()  argument
212 	new_mask = dw_readl(dws, DW_SPI_IMR) | mask;  in spi_umask_intr()
213 	dw_writel(dws, DW_SPI_IMR, new_mask);  in spi_umask_intr()
221 static inline void spi_reset_chip(struct dw_spi *dws)  in spi_reset_chip()  argument
223 	spi_enable_chip(dws, 0);  in spi_reset_chip()
224 	spi_mask_intr(dws, 0xff);  in spi_reset_chip()
225 	spi_enable_chip(dws, 1);  in spi_reset_chip()
228 static inline void spi_shutdown_chip(struct dw_spi *dws)  in spi_shutdown_chip()  argument
230 	spi_enable_chip(dws, 0);  in spi_shutdown_chip()
231 	spi_set_clk(dws, 0);  in spi_shutdown_chip()
246 extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws);
247 extern void dw_spi_remove_host(struct dw_spi *dws);
248 extern int dw_spi_suspend_host(struct dw_spi *dws);
249 extern int dw_spi_resume_host(struct dw_spi *dws);
252 extern int dw_spi_mid_init(struct dw_spi *dws); /* Intel MID platforms */